HD6437020 Datasheet, PDF (503/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

19.3.8 Serial Communications Interface Timing
Table 19.13 Serial Communications Interface Timing
Case A: V_CC = 3.0 to 5.5 V, V_SS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C*
Case B: V_CC = 5.0 V ±10%, V_SS = 0 V, φ = 16.6 MHz, Ta = –20 to +75°C*
Case C: V_CC = 5.0 V ±10%, V_SS = 0 V, φ = 20 MHz, Ta = –20 to +75°C*
*: Normal products: Ta = –40 to +85°C for wide-temperature range products.
Item
Symbol
Input clock cycle
Input clock cycle (clocked synchronization)
Input clock pulse width
Input clock rise time
Input clock fall time
Transmission data delay time (clocked
synchronization)
t_scyc
t_scyc
t_sckw
t_sckr
t_sckf
t_TXD
Receive data setup time (clocked
t_RXS
synchronization)
Receive data hold time (clocked
synchronization)
t_RXH
Cases A, B and C
Min
Max
Unit
4
—
t_cyc
6
—
t_cyc
0.4
0.6
t_scyc
—
1.5
t_cyc
—
1.5
t_cyc
—
100
ns
Figure
19.40
19.41
100
—
ns
100
—
ns
t_SCKW
SCK0, SCK1
t_SCKr
t_SCKf
t_scyc
Figure 19.40 Input Clock Timing
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