HD6437020 Datasheet, PDF (477/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

T_p
CK
A21–A0
RAS
CAS
RD(Read)
WRH, WRL,
(Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
RD(Write)
WRH, WRL,
(Write)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
WAIT
T_r
T_c1
T_w
T_c2
Row
Column
t_RDD
t_CAC2*¹
t_ACC2*²
t_RAC2*³
t_RSD
t_WTS t_WTH t_WTS t_WTH
Notes: 1.
2.
3.
For t_CAC2, use t_cyc × (n + 1) – 25 instead of t_cyc × (n + 1) – t_CASD2 – t_RDS.
For t_ACC2, use t_cyc × (n + 2) – 30 instead of t_cyc × (n + 2) – t_AD – t_RDS.
For t_RAC2, use t_cyc × (n + 2.5) – 20 instead of t_cyc × (n + 2.5) – t_RASD1 – t_RDS.
Figure 19.15 DRAM Bus Cycle: (Long Pitch, High-Speed Page Mode + Wait State)
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