HD6437020 Datasheet, PDF (441/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Section 17 RAM
17.1 Overview
The SH7020 and SH7021 has 1-kbytes of on-chip RAM. The on-chip RAM is linked to the CPU
and direct memory access controller (DMAC) with a 32-bit data bus (figure 17.1). The CPU can
access data in the on-chip RAM in byte, word, or long word units. The DMAC can access byte or
word data. On-chip RAM data can always be accessed in one state, making the RAM ideal for use
as a program area, stack area, or data area, which require high-speed access. The contents of the
on-chip RAM are held in both the sleep and standby modes. Memory area 7 addresses H'FFFFC00
to H'FFFFFFF are allocated to the on-chip RAM.
Internal data bus (32 bits)
H'FFFFC00
H'FFFFC04
H'FFFFC01
H'FFFFC05
H'FFFFC02
H'FFFFC06
H'FFFFC03
H'FFFFC07
H'FFFFFFC
On-chip RAM
H'FFFFFFD
H'FFFFFFE
H'FFFFFF
Figure 17.1 Block Diagram of RAM
17.2 Operation
Accesses to addresses H'FFFFC00–H'FFFFFFF are directed to the on-chip RAM. Memory area 7
(H'F000000–H'FFFFFFF) is divided into shadows in 1 kbyte units. All shadow accesses are on-
chip RAM accesses. For more information on shadows, see section 8, Bus State Controller.
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