HD6437020 Datasheet, PDF (219/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

• DREQ pin sampling timing in the burst mode
In the burst mode, the sampling timing differs depending on whether DREQ is detected by
edge or level.
When DREQ input is being detected by edge, once the falling edge of the DREQ signal is
detected, the DMA transfer continues until the transfer end conditions are satisfied, regardless
of the status of the DREQ pin. No sampling happens during this time. After the transfer ends,
sampling occurs every state until the TE bit of the CHCR is cleared.
When DREQ input is being detected by level, once the DREQ input is detected, next sampling
is performed at the end of every CPU or DMAC bus cycle in the single address mode. In the
dual address mode, the next sampling is performed at the start of every DMAC read cycle. In
both the single address mode and dual address mode, if no DREQ input is detected at this time,
sampling thereafter occurs at every state.
Figures 9.23 and 9.24 show the DREQ pin sampling timing in burst mode when DREQ input is
detected by low level.
CK
DREQ
Bus
cycle ^CPU
CPU
CPU
DMAC
DMAC
DMAC
CPU
DACK
Note: Single address DREQ level detection, DACK active low, 1 bus cycle = 2 states.
Figure 9.23 DREQ Pin Sampling Timing in Burst Mode
204 HITACHI