HD6437020 Datasheet, PDF (351/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

12.3.4 Timing of Setting the Overflow Flag (OVF)
In the interval timer mode, when the TCNT overflows the OVF flag is set to 1 and an interval
timer interrupt is requested (figure 12.6).
CK
TCNT
Overflow signal
(internal signal)
H'FF H'00
OVF
Figure 12.6 Timing of Setting the OVF
12.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When the TCNT overflows the WOVF bit of the RSTCSR is set to 1 and a WDTOVF signal is
output. When the RSTE bit is set to 1, TCNT overflow enables an internal reset signal to be
generated for the entire chip (figure 12.7).
CK
TCNT
Overflow signal
(internal signal)
H'FF H'00
WOVF
Figure 12.7 Timing of Setting the WOVF Bit and Internal Reset
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