HD6437020 Datasheet, PDF (54/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Table 2.14 Logic Operation Instructions
Instruction
Instruction Code
AND Rm,Rn
0010nnnnmmmm1001
AND #imm,R0
11001001iiiiiiii
AND.B #imm,@(R0,GBR) 11001101iiiiiiii
NOT
OR
OR
OR.B
Rm,Rn
0110nnnnmmmm0111
Rm,Rn
0010nnnnmmmm1011
#imm,R0
11001011iiiiiiii
#imm,@(R0,GBR) 11001111iiiiiiii
TAS.B @Rn
0100nnnn00011011
TST Rm,Rn
0010nnnnmmmm1000
TST #imm,R0
11001000iiiiiiii
TST.B #imm,@(R0,GBR) 11001100iiiiiiii
XOR Rm,Rn
0010nnnnmmmm1010
XOR #imm,R0
11001010iiiiiiii
XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
Operation
Execution
Cycles
Rn & Rm → Rn
1
R0 & imm → R0
1
(R0 + GBR) & imm → 3
(R0 + GBR)
~Rm → Rn
1
Rn | Rm → Rn
1
R0 | imm → R0
1
(R0 + GBR) | imm → (R0 3
+ GBR)
If (Rn) is 0, 1 → T; 1 → 4
MSB of (Rn)
Rn & Rm; if the result is 1
0, 1 → T
R0 & imm; if the result is 1
0, 1 → T
(R0 + GBR) & imm; if the 3
result is 0, 1 → T
Rn ^ Rm → Rn
1
R0 ^ imm → R0
1
(R0 + GBR) ^ imm →
3
(R0 + GBR)
T bit
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Test
result
Test
result
Test
result
Test
result
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HITACHI 35