HD6437020 Datasheet, PDF (182/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Read cycle Write cycle
Cycle during which bus is
not released (1 bus cycle)
Figure 8.45 TAS Instruction Read Cycle and Write Cycle
(c) Refresh cycle + bus cycle
The bus is never released during a refresh cycle and the following bus cycle ((a) or (b)
above)) (figure 8.46).
Refresh cycle 1 bus cycle
Cycle during which bus
is not released
Figure 8.46 Refresh Cycle and Following Bus Cycle
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