HD6437020 Datasheet, PDF (104/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

6.5.3 Instruction Fetch Break
If a break is attempted at the task A return destination instruction fetch, task B is activated before
the UBC interrupt by interrupt B generated during task A processing, and the UBC interrupt is
handled after the interrupt B exception handling.
(1) Cause
The SH7032/SH7034 chip operates as follows.
Interrupt B accepted
UBC interrupt accepted
Interrupt exception
handling
F DE E MMEME E
F
Interrupt exception
handling
Break
condition
<Address> <Description>
F D E EMM E ME E
0x00011a0a Instruction replaced by interrupt
exception handling
f
0x00011a0c Overrun fetch
0xf000974 Task B first instruction fetch
(instruction replaced by interrupt
exception handling)
F
(0xf000978 Overrun fetch)
0x02000030 UBC first instruction fetch
Figure 6.3
UBC Operation
It actually takes at least two cycles for the UBC interrupt generated by the address 0x00011a0c
instruction fetch cycle to be sent to the interrupt controller and interrupt exception handling to
begin. However, as shown in figure 6.3, when the UBC interrupt is generated, previously
generated interrupt B initiated by task B is accepted first, and the UBC interrupt is accepted after
completion of the interrupt B exception handling.
(2) Remedy
There is no way of preventing this operation by hardware. A software solution, such as the use of
a flag, must be employed.
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