TLK3132 Datasheet, PDF (97/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
8 Bit SERDES Mode - Continuous Mode - Jitter Cleaner (1x) Mode
SERDES RATE [1:0] (See Note 2 Below)
REFCLK (Mhz)
REF_DIV[6:0] FB_DIV[6:0]
4/5.37124:14:8 4/5.37124:6:0 PLL_MULT[3:0] RXTX_DIV[6:0]
2'b00 (Full)
2'b01 (Half)
2'b10 (Quarter)
Min
Max
(Decimal)
(Decimal) See Note 1 Below 4/5.37125:6:0 Min
Max
Min
Max
Min
Max
125.0000 130.2083
1
24
8
24
2000.000 2083.333 1000.000 1041.667 500.000 520.833
127.1739 135.8696
1
23
8
23
2034.783 2173.913 1017.391 1086.957 508.696 543.478
132.9545 142.0455
1
22
8
22
2127.273 2272.727 1063.636 1136.364 531.818 568.182
139.2857 148.8095
1
21
8
21
2228.571 2380.952 1114.286 1190.476 557.143 595.238
146.2500 156.2500
1
20
8
20
2340.000 2500.000 1170.000 1250.000 600.000 625.000
153.9474 164.4737
1
19
8
19
2463.158 2631.579 1231.579 1315.789 615.789 657.895
162.5000 173.6111
1
18
8
18
2600.000 2777.778 1300.000 1388.889 650.000 694.444
172.0588 183.8235
1
17
8
17
2752.941 2941.176 1376.471 1470.588 688.235 735.294
182.8125 195.3125
1
16
8
16
2925.000 3000.000 1462.500 1562.500 731.250 781.250
195.0000 200.0000
1
15
8
15
3120.000 3200.000 1560.000 1600.000 780.000 800.000
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
A. Note that REFCLK is limited to 187.5 MHz when in Full rate mode to achieve 3000 Mbps serial data rate.
Figure A-7. 8 BIT SERDES Mode – Jitter Cleaner/SERDES (1x) Provisioning^(A)
8 Bit SERDES Mode - Continuous Mode - Jitter Cleaner (0.5x) Mode
SERDES RATE [1:0] (See Note 2 Below)
REFCLK (Mhz)
REF_DIV[6:0] FB_DIV[6:0]
4/5.37124:14:8 4/5.37124:6:0 PLL_MULT[3:0] RXTX_DIV[6:0]
2'b00 (Full)
2'b01 (Half)
2'b10 (Quarter)
Min
Max
(Decimal)
(Decimal) See Note 1 Below 4/5.37125:6:0
Min
Max
Min
Max
Min
Max
250.0000 260.4167
4
48
8
24
2000.000 2083.333 1000.000 1041.667 500.000 520.833
254.3478 271.7391
4
46
8
23
2034.783 2173.913 1017.391 1086.957 508.696 543.478
265.9091 284.0909
4
44
8
22
2127.273 2272.727 1063.636 1136.364 531.818 568.182
278.5714 297.6190
4
42
8
21
2228.571 2380.952 1114.286 1190.476 557.143 595.238
292.5000 312.5000
4
40
8
20
2340.000 2500.000 1170.000 1250.000 600.000 625.000
307.8947 328.9474
4
38
8
19
2463.158 2631.579 1231.579 1315.789 615.789 657.895
325.0000 347.2222
4
36
8
18
2600.000 2777.778 1300.000 1388.889 650.000 694.444
344.1176 367.6471
4
34
8
17
2752.941 2941.176 1376.471 1470.588 688.235 735.294
365.6250 375.0000
4
32
8
16
2925.000 3000.000 1462.500 1500.000 731.250 750.000
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
Figure A-8. 8 BIT SERDES Mode – Jitter Cleaner/SERDES (0.5x) Provisioning
A.1 Recovered Byte Clock Jitter Cleaner Mode:
If it is desired to dedicate the Jitter Cleaner PLL to clean the RX SERDES recovered byte clock, then the
following procedure must be followed:
1. Program REF_SEL[1:0] to 2’b10.
2. Program RXB_SEL[1:0] to 2’b00.
3. Program RX_SEL to 2’b10 -or- 2’b11.
4. Program TX_SEL as desired.
5. Program 16.10:9 as desired on a per channel basis.
6. Consult the rows in the appropriate Appendix A table to find the appropriate REFCLK and SERDES
mode settings. Note that only rows indicating that the Jitter Cleaner PLL is OFF may be used.
Provision the SERDES settings appropriately.
7. Divide the selected SERDES serial rate by 8 if in EBI/REBI modes, or 10 otherwise, and use that
frequency as the input to Figure A-9 Recovered Byte Clock Jitter Cleaner Mode, to determine the
appropriate Jitter Cleaner PLL settings. Note that only a 1:1 frequency ratio is supported between the
SERDES output byte clock and the parallel interface output recovered byte clock. Depending upon the
selection of TX_SEL, it may also be necessary to provision RXTX_DIV with the same value as
RXB_DIV.
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APPENDIX A – Frequency Ranges Supported
97