TLK3132 Datasheet, PDF (77/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
TIMING
MODE
NAME
NBID
Table 4-2. Parallel Interface – Valid Signal Operational Mode Definitions (continued)
USAGE MODE
Nine Bit Interface DDR Mode (NBID)
(Un-encoded Data Byte + 1 Control Bit)
DDR Timing Support
See Section 4.11: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.13: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In NBID Mode
CH0: TX Control Bit = TXC_[0]
CH1: TX Control Bit = TXC_[1]
CH0: RX Control Bit = RXC_[0]
CH1: RX Control Bit = RXC_[1]
TX SIGNALS USED
TXDATA = TXC_ [0], TXD[7:0]
TXCLK = TXCLK_ [0]
OR
TXDATA = TXC_ [1], TXD[15:8]
TXCLK = TXCLK_ [1]
RX SIGNALS USED
RXDATA = RXC_ [0], RXD[7:0]
RXCLK = RXCLK_ [0]
OR
RXDATA = RXC_ [1], RXD[15:8]
RXCLK = RXCLK_ [1]
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Electrical Specifications
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