TLK3132 Datasheet, PDF (63/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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3.4 Signal Pin Description
TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
SIGNAL LOCATION VOLTAGE
RST_N
N1
VDDO
ENABLE
M2
VDDO
SPEED[1:0]
F2
J14
VDDO
PLOOP
M13
VDDO
SLOOP
J13
VDDO
PRBS_EN
M1
VDDO
CODE
K3
VDDO
Table 3-1. Global Signals
TYPE
2.5 V
LVCMOS
Input
2.5 V
LVCMOS
Input
2.5 V
LVCMOS
Input
DESCRIPTION
Chip Reset (Active Low) When asserted (low logic level), this signal reinitializes
the entire device. Must be held asserted (low logic level) for at least 10 µS after
device power up.
Device Enable.
When this pin is held low, the device is in a low power state.
When high the device operates normally.
A hard or soft reset must be applied after a change of state occurs on this input
signal.
Speed Selection pins. These pins put all four channels of TLK3132 into one of
the three supported (full/half/quarter) operation speeds.
00 – Both channels in Full Rate mode
01 – Both channels in Half Rate mode
10 – Both channels in Quarter rate mode
11 – Software Selectable Rate
In the software selectable rate mode, the rate may be configured independently
by the MDIO interface.
The SPEED[1:0] inputs control both RX and TX directions.
See Appendix A for further information on speed selection (full/half/quarter) for
proper settings as a function of the application mode and reference clock
frequency.
2.5 V
LVCMOS
Input
2.5 V
LVCMOS
Input
2.5 V
LVCMOS
Input
2.5 V
LVCMOS
Input
Note that if these pins are not configured on the application board to select
“Software Selectable Rate”, then the internal speed register bits cannot be used
to control the rate settings, and the full/half/quarter rate selection is fixed.
Parallel Loop Enable. When high, the serial output is internally looped back to
the serial input so that the transmit parallel interface input data is output onto the
receive parallel interface.
Serial Loop Enable. When high, the serial input is internally looped back to the
serial output, making a serial repeater. In device configurations where clock
tolerance compensation is not performed in the transmit direction, there are two
options for error free serial loopback operation:
1. Frequency lock (0 ppm) the incoming serial data rate to the local reference
clock device input.
2. Provision the TX SERDES REFCLK to run from a jitter cleaned version of the
RX SERDES RXBCLK (Receive Byte Clock).
PRBS Enable. When this pin is asserted high, the internal PRBS generator and
comparator circuits are enabled on the transmit and receive data paths. The
PRBS results can be read through MDIO counters. Primary chip output signals
GPO0/GPO1 remain low during PRBS testing when the input serial stream PRBS
pattern is correct, and pulses high when PRBS errors are detected on the input
serial stream.
GPO1 contains the Channel 1 PRBS currently passing (when low) indication.
GPO0 contains the Channel 0 PRBS currently passing (when low) indication.
An external loopback connection (via external cables) is required during PRBS
testing.
PRBS 2⁷-1 is transmitted on each transmit channel serial output, and compared
on each receive channel serial input.
Code Enable. This signal is logically ORed with the PCS_EN register bit
(Register Bit 17.3). RGMII/GMII applications can either tie this input signal high
(preferred) or tie this signal low (must program the PCS_EN 17.3 register bit after
device reset to high if CODE is tied off low). Non RGMII/GMII applications must
tie this input signal low.
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Device Reset Requirements/Procedure
63