TLK3132 Datasheet, PDF (7/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
2-40 Output Swing Control............................................................................................................. 42
2-41 SERDES_TEST_CONFIG_TX .................................................................................................. 43
2-42 SERDES_TEST_CONFIG_RX .................................................................................................. 43
2-43 SERDES_RX0_STATUS......................................................................................................... 44
2-44 SERDES_RX1_STATUS......................................................................................................... 44
2-45 SERDES_TX0_STATUS ......................................................................................................... 44
2-46 SERDES_TX1_STATUS ......................................................................................................... 44
2-47 SERDES_PLL_STATUS ......................................................................................................... 44
2-48 JC_CLOCK_MUX_CONTROL .................................................................................................. 45
2-49 JC_VTP_CLK_DIV_CONTROL ................................................................................................. 45
2-50 JC_DELAY_STOPWATCH_CLK_DIV_CONTROL........................................................................... 46
2-51 JC_DELAY_STOPWATCH_COUNTER ....................................................................................... 46
2-52 JC_REFCLK_FB_DIV_CONTROL.............................................................................................. 46
2-53 JC_RXB_OUTPUT_CLK_DIV_CONTROL .................................................................................... 46
2-54 JC_CHARGE_PUMP_CONTROL .............................................................................................. 47
2-55 Charge Pump Control Setting (CP_CTRL) .................................................................................... 47
2-56 JC_PLL_CONTROL .............................................................................................................. 47
2-57 JC_TEST_CONTROL_1 ......................................................................................................... 48
2-58 JC_TEST_CONTROL_2 ......................................................................................................... 48
2-59 JC_TI_TEST_CONTROL_1 ..................................................................................................... 48
2-60 JC_TI_TEST_CONTROL_2 ..................................................................................................... 48
2-61 JC_TRIM_STATUS ............................................................................................................... 48
2-62 DIE_ID_7 ........................................................................................................................... 48
2-63 DIE_ID_6 ........................................................................................................................... 48
2-64 DIE_ID_5 ........................................................................................................................... 49
2-65 DIE_ID_4 ........................................................................................................................... 49
2-66 DIE_ID_3 ........................................................................................................................... 49
2-67 DIE_ID_2 ........................................................................................................................... 49
2-68 DIE_ID_1 ........................................................................................................................... 49
2-69 DIE_ID_0 ........................................................................................................................... 49
2-70 EFUSE_STATUS ................................................................................................................. 49
2-71 EFUSE_CONTROL ............................................................................................................... 49
2-72 HSTL_INPUT_TERMINATION_CONTROL ................................................................................... 50
2-73 HSTL_OUTPUT_SLEWRATE_CONTROL .................................................................................... 50
2-74 HSTL_INPUT_VTP_CONTROL................................................................................................. 50
2-75 HSTL_OUTPUT_VTP_CONTROL.............................................................................................. 51
2-76 HSTL_GLOBAL_CONTROL..................................................................................................... 51
2-77 TX0_DLL_CONTROL............................................................................................................. 52
2-78 TX1_DLL_CONTROL............................................................................................................. 52
2-79 RX0_DLL_CONTROL ............................................................................................................ 52
2-80 RX1_DLL_CONTROL ............................................................................................................ 52
List of Tables
7