TLK3132 Datasheet, PDF (3/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
4.10.1 PARAMETER MEASUREMENT .............................................................................. 74
4.11 HSTL Output Switching Characteristics (DDR Timing Mode Only).................................................. 78
4.12 HSTL Output Switching Characteristics (SDR Timing Mode Only) .................................................. 79
4.13 HSTL (DDR Timing Mode Only) Input Timing Requirements ........................................................ 80
4.14 HSTL (SDR Timing Mode Only) Input Timing Requirements ........................................................ 81
4.15 MDIO Timing Requirements Over Recommended Operating Conditions .......................................... 82
4.16 JTAG Timing Requirements Over Recommended Operating Conditions .......................................... 83
Package Dissipation Rating............................................................................................... 85
A APPENDIX A – Frequency Ranges Supported........................................................................ 87
A.1 Recovered Byte Clock Jitter Cleaner Mode:............................................................................ 97
B APPENDIX B – Jitter Cleaner PLL External Loop Filter............................................................ 99
C APPENDIX C – Device Test Mode ....................................................................................... 100
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