TLK3132 Datasheet, PDF (21/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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2.7.4 GMII Mode (Gigabit Media Independent Interface)
TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
DATA
CHANNEL
NUMBER
Channel 0
Channel 1
TX_EN
CONTROL
BIT
(INPUT)
TXC_[0]
TXC_[1]
Table 2-6. GMII – Lane To Functional Pin Mapping
TX_ER
CONTROL
BIT
(INPUT)
TXC_[4]
TXC_[5]
TRANSMIT
DATA BYTE
(INPUT)
TXD_[7:0]
TXD_[15:8]
RX_DV
CONTROL
BIT
(OUTPUT)
RXC_[0]
RXC_[1]
RX_ER
RECEIVE
CONTROL BIT DATA BYTE
(OUTPUT) (OUTPUT)
RXC_[4]
RXC_[5]
RXD_[7:0]
RXD_[15:8]
TRANSMIT
CLOCK
(INPUT)
TXCLK_[0]
TXCLK_[1]
RECEIVE
CLOCK
(OUTPUT)
RXCLK_[0]
RXCLK_[1]
TXCLK_[0]
SDR Rising Edge Aligned Timing
TXC_[0],TXC_[4],TXD_[7:0]
{TX_EN,TX_ER,Data0[7:0]}
{TX_EN,TX_ER,Data1[7:0]}
RXCLK_[0]
RXC_[0],RXC_[4],RXD_[7:0]
TXCLK_[0]
TXC_[0],TXC_[4],TXD_[7:0]
{RX_DV,RX_ER,Data0[7:0]}
{RX_DV,RX_ER,Data1[7:0]}
SDR Falling Edge Aligned Timing
{TX_EN,TX_ER,Data0[7:0]}
{TX_EN,TX_ER,Data1[7:0]}
RXCLK_[0]
RXC_[0],RXC_[4],RXD_[7:0]
{RX_DV,RX_ER,Data0[7:0]}
{RX_DV,RX_ER,Data1[7:0]}
Figure 2-11. GMII – Individual Channel Byte Ordering – Channel 0 Example
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