TLK3132 Datasheet, PDF (10/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
www.ti.com
1.3 Description
The TLK3132 is a flexible two channel independently configurable serial transceiver. It can be configured
to be compliant with the 1000Base-X 1Gbps Ethernet Specification (Auto-Negotiation not supported). The
TLK3132 provides high-speed bi-directional point-to-point data transmissions with up to 15 Gbps of raw
data transmission capacity. The primary application of this device is in backplanes and front panel
connections requiring 3.75Gbps connections over controlled impedance media of approximately 50Ω. The
transmission media can be printed circuit board (PCB) traces, copper cables or fiber-optical media. The
ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media
and the noise coupling into the lines.
The TLK3132 performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions
for a physical layer interface. The TLK3132 also provides 1000Base-X (PCS) layer functionality described
in Clause 36 of 802.3-2002. The serial transmitter is implemented using differential Current Mode Logic
(CML) with integrated termination resistors.
Figure 1-1 shows an example system block diagram for TLK3132 used to provide the Physical Coding
Sublayer to Coarse Wave-length Division Multiplexed optical transceiver or parallel optics.
Many common applications may be enabled by way of externally available control pins. Detailed control of
the TLK3132 on a per channel basis is available by way of accessing a register space of control bits
available through a two-wire access port called the Management Data Input/Output (MDIO) interface.
The PCS (Physical Coding Sublayer) functions such as the CTC FIFO are designed to be compliant for a
1000Base-X PCS link. However, each of the PCS functions may be disabled or bypassed until the
TLK3132 is operating at its most basic state, that of a simple two channel 10-bit SERDES suitable for a
wide range of applications such as CPRI or OBSAI wireless infrastructure links.
The differential output swing for the TLK3132 is suitable for compliance with IEEE 802.3 Gigabit Ethernet
links, which is also suitable for CPRI LV serial links. The TLK3132 provides for setting larger output signal
swing suitable for CPRI HV links by setting an appropriate register bit available though MDIO.
Line Card
2
TLK3132
2
MAC/
Packet
Processor
TXCLK[1:0]
2
TXD(15:0)
2
TXC(5:4,1:0)
TLK3132
CWDM or
Parallel
Optics
RXC(5:4,1:0)
RXCLK[1:0]
RXD(15:0)
Figure 1-1. System Block Diagram – PCS
10
Introduction
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