TLK3132 Datasheet, PDF (47/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
Table 2-54. JC_CHARGE_PUMP_CONTROL⁽¹⁾
ADDRESS: 0x9106
DEFAULT: 0x00C0
BIT(s)
NAME
DESCRIPTION
37126.15:14 CP_BUF_CTRL[1:0] Charge pump buffer control
37126.13:0 CP_CTRL[13:0]
Charge pump control. When JC PLL is used, CP_CTRL[13:0] values need to be set
according to FB_DIV[6:0] range. Refer to Table 2-55: Charge Pump Control Setting
(CP_CTRL)
ACCESS
RW
RW
(1) When JC PLL is used, this register value should be set according to the values specified in Charge Pump Control Setting Table.
Table 2-55. Charge Pump Control Setting (CP_CTRL)
FB DIV VALUE RANGE
(37124[6:0]) (in decimal)
1 - 15
16 - 18
19 - 30
31 - 33
34 - 45
46 - 53
54 - 59
60 - 68
69 - 77
78 - 85
86 - 88
89 - 91
92 - 99
100 - 107
108 - 113
114 - 127
JC_CHARGE_PUMP_ CONTROL SETTING
(37126 [15:0])
0x00FF
0x00C1
0x0081
0x017F
0x017D
0x011F
0x0151
0x0121
0x01C3
0x0101
0x02FB
0x0183
0x0237
0x0181
0x0261
0x0215
BIT(s)
37127.15
37127.14:12
37127.11:8
37127.7
37127.6
37127.5:4
37127.3
37127.2
Table 2-56. JC_PLL_CONTROL
ADDRESS: 0x9107
NAME
JC_EN_PLL
VCO_BIAS_CTRL[2:0]
VCO_CAPBANK_CTRL[3:0]
DIFFTX_EN
DIFFRX_EN
PFD_CTRL[1:0]
AD_SEL_TST
REFCLK_CML_EN
DEFAULT: 0x30C4
DESCRIPTION
0 = Disables Jitter Cleaner
1 = Enables Jitter Cleaner
Control bits for VCO tail current
Control bits for VCO band select
Enable signal for TX differential path
Enable signal for RX differential path
Control bits for phase frequency detector
Control bit to select either digital or analog TST_OUT
Enable signal for CML buffer inside output divider
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
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