TLK3132 Datasheet, PDF (31/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
2.7.15 High Speed Receiver
The high speed receiver conforms to the physical layer requirements of IEEE 802.3ae Clause 47(XAUI),
Gigabit Ethernet, and FibreChannel 1 and 2. Register control gives selection between AC and DC
coupling at the receiver. When the receiver is AC coupled, the termination impedances of the receivers
are configured as 100 Ω with the center tap weakly tied to 0.8×VDDT with a capacitor to create an AC
ground. When the receiver is DC coupled, the common mode will be determined by both receiver and
transmitter characteristics.
All receive channels incorporate an adaptive equalizer. This circuit compensates for channel insertion loss
by amplifying the high frequency components of the signal, reducing inter-symbol interference.
Equalization can be enabled or disabled per register settings. Both the gain and bandwidth of the
equalizer are controlled by the receiver equalization logic. There are ten available equalization settings.
2.7.16 Loopback
In independent channel mode, channels can independently be configured for parallel or serial side
loopback.
An external loopback (requiring external connection) is also supported, which can be used with the PRBS
patterns, as well as the CRPAT, Mixed/High/Low Frequency tests.
2.7.17 Link Test Functions
The TLK3132 has an extensive suite of built in test functions to support system diagnostic requirements.
Each channel has built-in link test generator and verification logic. Several patterns can be selected via
the MDIO that offer extensive test coverage. The patterns are: 2⁷-1 or 2²³-1 PRBS (Pseudo Random Bit
Stream), CRPAT, high and low and mixed frequency patterns.
2.7.18 MDIO Management Interface
The TLK3132 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of
the IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the
serial links. Normal operation of the TLK3132 is possible without use of this interface. However, some
additional features are accessible only through the MDIO.
The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference
(MDC). The device id and port address are determined by control pins (see Table 3-3).
In Clause 22, the top 4 control pins PRTAD[4:1] determine the device port address. In this mode the 2
individual channels in the TLK3132 are classified as 2 different ports. So for any PRTAD[4:1] value there
will be 2 ports per TLK3132.
The TLK3132 will respond if the 4 MSBs of the PHY address field on the MDIO protocol (PA[4:1]) matches
PRTAD[4:1]. The LSB of the PHY address field (PA[0]) will determine which channel/port within TLK3132
to respond to:
If PA[0] = 1b0, TLK3132 Channel 0 will respond.
If PA[0] = 1b1, TLK3132 Channel 1 will respond.
Write transactions which address an invalid register or device or a read only register will be ignored. Read
transactions which address an invalid register will return a 0.
2.7.19 MDIO Protocol Timing
The Clause 22 timing required to read from the internal registers is shown in Figure 2-22. The Clause 22
timing required to write to the internal registers is shown in Figure 2-23.
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