TLK3132 Datasheet, PDF (54/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
www.ti.com
BIT(s)
38400.15
38400.11:10
38400.7
38400.3
Table 2-88. STCI_CONTROL_STATUS
ADDRESS: 0x9600
NAME
STCI_CLK
STCI_CFG[1:0]
STCI_D
STCI_Q
DEFAULT: 0x0000
DESCRIPTION
Bit to generate STCI clock in functional mode.
STCI CFG control
STCI data in
STCI read data
ACCESS
RW
RO
BIT(s)
38401.15
ADDRESS: 0x9601
NAME
TESTCLKT
Table 2-89. TESTCLK_CONTROL
DEFAULT: 0x0000
DESCRIPTION
Bit to generate TESTCLKT clock in functional mode.
For TI test purposes only.
ACCESS
RW
BIT(s)
38656.15
Table 2-90. BIDI_CMOS_CONTROL
ADDRESS: 0x9700
NAME
MDIO Disable Comp Test
Control
DEFAULT: 0x0000
DESCRIPTION
0 = MDIO/MDC Bidi cells automatically detects operating voltage (default)
1 = MDIO/MDC Bidi cells expects 2.5 V operating voltage
ACCESS
RW
BIT(s)
38912:8
38912.7
38912.4:0
ADDRESS: 0x9800
NAME
DEBUG_SEL_EN
DIG_TST_OUT_EN
DEBUG_SEL
Table 2-91. DEBUG_CONTROL
DEFAULT: 0x001F
DESCRIPTION
1 = Sends debug status signals onto debug outputs (GPO)
0 = Debug outputs are tied to 0.
For TI test purposes only.
1 = Enables sending DIG TST debug signal onto GPO4
0 = Disables sending DIG TST debug signal onto GPO4.
For TI test purposes only.
Debug select bits. For TI test purposes only.
ACCESS
RW
BIT(s)
39168.15
Table 2-92. DUTY_CYCLE_CONTROL
ADDRESS: 0x9900
DEFAULT: 0x0000
NAME
DESCRIPTION
Duty Cycle
Correction
Bypass
1 = Bypasses duty cycle corrected RX/TXBCLK. (Duty cycle set to 40-60, same clocks as
SERDES parallel launch and capture clocks)
0 = Uses duty cycle corrected RX/TXBCLK. (Duty cycle set to 50-50, no phase relationship to
SERDES parallel launch and capture clock)(default). For TI test purposes only.
ACCESS
RW
54
Detailed Description
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