TLK3132 Datasheet, PDF (11/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

www.ti.com
TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
REFCLK_P
REFCLK_N
REFCLK
RXBCLK[0]
REF_SEL[1:0]
00
REFCLK
01
Divider
REF_DIV[6:0]
1X
Jitter Cleaner
PLL Core
PLL
Feedback
Divider
FB_DIV[6:0]
HSTL_2X_CLK
00
RXBYTE_CLK
01
10
11
RXB_SEL[1:0]
00
DELAY_CLK
01
10
11
DEL_SEL[1:0]
00
HSTL Output
Divider
01
HSTL_DIV2[6:0]
10
11
HSTL_SEL[1:0]
Second PLL
Output
Divider
RXB_DIV[6:0]
Third PLL
Output
Divider
DEL_DIV[6:0]
Fourth PLL
Output
Divider
HSTL_DIV1[6:0]
First PLL Output
Divider
RXTX_DIV[6:0]
TX_SEL[1:0]
SERDES TX
00
01 REFCLK_TX
PLL
10
P2S
11
P2S
SERDES RX
00
01 REFCLK_RX _PLL
10
S2P
11
S2P
TX1P/N
TX0P/N
RX1P/N
RX0P/N
RX_SEL[1:0]
(2.875 Ghz Min., 3 Ghz Typ., 3.125 Ghz Max.)
Note: Default Mux Selects are Underlined.
Figure 1-2. Block Diagram – TLK3132 Clocking Architecture
2 Detailed Description
2.1 Clocking Modes
The TLK3132 contains an internal low-bandwidth, low-jitter high quality LC oscillator that may be
configured as a jitter cleaner. The jitter cleaner oscillator has a high frequency narrow band of operation
that may be used to generate all common reference clock frequencies by way of programmable pre-scaler
and post-scaler registers. In this manner a poor quality input reference clock can be input to the jitter
cleaner which will lock to the reference clock and provide a clean reference to the internal SERDES PLLs.
Appendix A defines in detail the clocking possibilities, and device settings.
Alternatively, the jitter cleaner may be used to lock to a recovered byte clock from RX channel 0 and
remove jitter that may have transferred through the clock/data recovery circuit from the serial data stream
to the recovered byte clock (including parallel output data timing). In this way the recovered byte clock
may be extracted from the serial data stream yet be suitable for use in applications that require a clean
clock source derived from the serial data stream. The TLK3132 jitter cleaner may only be used on the
recovered byte clock from Channel 0. If the jitter cleaner is used to clean the recovered byte clock, it may
not also be used to clean the input reference clock, and the PLL at the center of the deserializer core must
have a clean low-jitter reference clock from an external clock source, preferably a low-jitter crystal based
oscillator. Also note that the Transmit SERDES macro can run from the cleaned recovered RX channel 0
byte clock which allows for the outgoing TX serial data rate for all channels to exactly match the incoming
data rate of RX Channel 0.
The TLK3132 clocking architecture allows for bypass of the JC PLL in cases where power or application
board area is critical.
See Figure 1-2 Block Diagram – TLK3132 Clocking Architecture for a representation of the use of the jitter
cleaner in the TLK3132.
Submit Documentation Feedback
Detailed Description
11