TLK3132 Datasheet, PDF (81/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
4.14 HSTL (SDR Timing Mode Only) Input Timing Requirements
PARAMETER
TEST CONDITIONS
t_setup TXDATA setup prior to
TXCLK transition high
Falling Edge Aligned (Rising Edge Sampled) Data See Figure 4-11.
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise time on all
input signals.
t_hold TXDATA hold after TXCLK Falling Edge Aligned (Rising Edge Sampled) Data See Figure 4-11.
transition high
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise time on all
input signals.
t_setup TXDATA setup prior to
TXCLK transition low
Rising Edge Aligned (Falling Edge Sampled) Data See Figure 4-12.
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise time on all
input signals.
t_hold TXDATA hold after TXCLK Rising Edge Aligned (Falling Edge Sampled) Data See Figure 4-12.
transition low
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise time on all
input signals.
t_duty TXCLK Duty Cycle
Rising and Falling Edge Sampled Data
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise time on all
input signals.
t_period TXCLK Period
T_freq TXCLK Frequency
Rising and Falling Edge Aligned Data
Rising and Falling Edge Aligned Data
(1) All typical values are at 25°C and with a nominal supply.
MIN NOM⁽¹⁾
480
MAX UNIT
ps
480
ps
480
ps
480
ps
40%
60%
2.67
16.67 ns
60
375 MHz
TXCLK
t PERIOD
tSETUP
t HOLD
V_IH(ac)
VDDQ/2
V_IL(ac)
V_IH(ac)
TXDATA ^VDDQ/2
V _IL(ac)
Figure 4-11. HSTL (SDR Timing Mode Only) Falling Edge Aligned (Rising Edge Sampled) Data Input
Timing Requirements
TXCLK
V_IH(ac)
TXDATA VDDQ/2
V_IL(ac)
t_PERIOD
t_SETUP
t_HOLD
V_IH(ac)
VDDQ/2
V_IL(ac)
Figure 4-12. HSTL (SDR Timing Mode Only) Rising Edge Aligned (Falling Edge Sampled) Data Input
Timing Requirements
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Electrical Specifications
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