TLK3132 Datasheet, PDF (83/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

www.ti.com
TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
4.16 JTAG Timing Requirements Over Recommended Operating Conditions
(unless otherwise noted)
t_period
t_setup
t_hold
T_valid
PARAMETER
TCK period
TDI/TMS/TRST_N setup to ↑ TCK
TDI/TMS/TRST_N hold from ↑ TCK
TDO delay from TCK falling
TEST CONDITIONS
See Figure 4-14.
See Figure 4-14.
See Figure 4-14.
See Figure 4-14.
MIN
66.67
3
5
0
NOM MAX
5
UNIT
ns
ns
ns
ns
TCK
TDI/TMS/
TRST_N
t_PERIOD
t_SETUP
t_HOLD
t_VALID
TDO
Figure 4-14. JTAG Timing
50 W
OUTPUT
VDDQ
50 W transmission line
VDDQ
150/200/
300/Open
(W)
+
150/200/
300/Open
(W)
GND
-
RW
VREF
RW
GND
PCB
Figure 4-15. HSTL I/O Schematic
INPUT
Submit Documentation Feedback
Electrical Specifications
83