TLK3132 Datasheet, PDF (96/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
www.ti.com
9/10 Bit SERDES Mode - Continuous Mode - Jitter Cleaner (0.25X) Mode
SERDES RATE[1:0] (See Note 2 Below)
REFCLK (Mhz)
REF_DIV[6:0] FB_DIV[6:0]
4/5.37124:14:8 4/5.37124:6:0 PLL_MULT[3:0]
RXTX_DIV[6:0] ^{RATE[1:0] =2'b00 Full RATE[1:0] =2'b01 HalfRATE[1:0] =2'b10 Qrtr.}
Min
Max
(Decimal)
(Decimal) See Note 1 Below 4/5.37125:6:0
Min
Max
Min
Max
Min
Max
200.0000 211.8644
4
59
20
59
2000.000 2118.644 1000.000 1059.322 500.000 529.661
201.7241 215.5172
4
58
20
58
2017.241 2155.172 1008.621 1077.586 504.310 538.793
205.2632 219.2982
4
57
20
57
2052.632 2192.982 1026.316 1096.491 513.158 548.246
208.9286 223.2143
4
56
20
56
2089.286 2232.143 1044.643 1116.071 522.321 558.036
212.7273 227.2727
4
55
20
55
2127.273 2272.727 1063.636 1136.364 531.818 568.182
216.6667 231.4815
4
54
20
54
2166.667 2314.815 1083.333 1157.407 541.667 578.704
220.7547 235.8491
4
53
20
53
2207.547 2358.491 1103.774 1179.245 551.887 589.623
225.0000 240.3846
4
52
20
52
2250.000 2403.846 1125.000 1201.923 562.500 600.962
229.4118 245.0980
4
51
20
51
2294.118 2450.980 1147.059 1225.490 573.529 612.745
234.0000 250.0000
4
50
20
50
2340.000 2500.000 1170.000 1250.000 585.000 625.000
238.7755 255.1020
4
49
20
49
2387.755 2551.020 1193.878 1275.510 600.000 637.755
243.7500 260.4167
4
48
20
48
2437.500 2604.167 1218.750 1302.083 609.375 651.042
248.9362 265.9574
4
47
20
47
2489.362 2659.574 1244.681 1329.787 622.340 664.894
254.3478 271.7391
4
46
20
46
2543.478 2717.391 1271.739 1358.696 635.870 679.348
260.0000 277.7778
4
45
20
45
2600.000 2777.778 1300.000 1388.889 650.000 694.444
265.9091 284.0909
4
44
20
44
2659.091 2840.909 1329.545 1420.455 664.773 710.227
272.0930 290.6977
4
43
20
43
2720.930 2906.977 1360.465 1453.488 680.233 726.744
278.5714 297.6190
4
42
20
42
2785.714 2976.190 1392.857 1488.095 696.429 744.048
285.3659 304.8780
4
41
20
41
2853.659 3048.780 1426.829 1524.390 713.415 762.195
292.5000 312.5000
4
40
20
40
2925.000 3125.000 1462.500 1562.500 731.250 781.250
300.0000 320.5128
4
39
20
39
3000.000 3205.128 1500.000 1602.564 750.000 801.282
307.8947 328.9474
4
38
20
38
3078.947 3289.474 1539.474 1644.737 769.737 822.368
316.2162 337.8378
4
37
20
37
3162.162 3378.378 1581.081 1689.189 790.541 844.595
325.0000 347.2222
4
36
20
36
3250.000 3472.222 1625.000 1736.111 812.500 868.056
334.2857 357.1429
4
35
20
35
3342.857 3571.429 1671.429 1785.714 835.714 892.857
344.1176 367.6471
4
34
20
34
3441.176 3676.471 1720.588 1838.235 860.294 919.118
354.5455 375.0000
4
33
20
33
3545.455 3750.000 1772.727 1875.000 886.364 937.500
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
Figure A-5. 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (0.25x) Provisioning
8 Bit SERDES Mode - Continuous Mode - Jitter Cleaner (2x) Mode
SERDES RATE [1:0] (See Note 2 Below)
REFCLK (Mhz)
REF_DIV[6:0] FB_DIV[6:0]
4/5.37124:14:8 4/5.37124:6:0 PLL_MULT[3:0] RXTX_DIV[6:0]
2'b00 (Full)
2'b01 (Half)
2'b10 (Quarter)
Min
Max
(Decimal)
(Decimal) See Note 1 Below 4/5.37125:6:0 Min
Max
Min
Max
Min
Max
62.5000 65.1042
1
48
8
24
2000.000 2083.333 1000.000 1041.667 500.000 520.833
63.5870 67.9348
1
46
8
23
2034.783 2173.913 1017.391 1086.957 508.696 543.478
66.4773 71.0227
1
44
8
22
2127.273 2272.727 1063.636 1136.364 531.818 568.182
69.6429 74.4048
1
42
8
21
2228.571 2380.952 1114.286 1190.476 557.143 595.238
73.1250 78.1250
1
40
8
20
2340.000 2500.000 1170.000 1250.000 600.000 625.000
76.9737 82.2368
1
38
8
19
2463.158 2631.579 1231.579 1315.789 615.789 657.895
81.2500 86.8056
1
36
8
18
2600.000 2777.778 1300.000 1388.889 650.000 694.444
86.0294 91.9118
1
34
8
17
2752.941 2941.176 1376.471 1470.588 688.235 735.294
91.4063 97.6563
1
32
8
16
2925.000 3000.000 1462.500 1562.500 731.250 781.250
97.5000 100.0000
1
30
8
15
3120.000 3200.000 1560.000 1600.000 780.000 800.000
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
A. Note that REFCLK is limited to 93.75 MHz when in Full rate mode to achieve 3000 Mbps serial data rate.
Figure A-6. 8 BIT SERDES Mode – Jitter Cleaner/SERDES (2x) Provisioning^(A)
96
APPENDIX A – Frequency Ranges Supported
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