TLK3132 Datasheet, PDF (89/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
REFCLK Input
(MHz)
61.44000
61.44000
61.44000
61.44000
61.44000
122.88000
122.88000
122.88000
122.88000
122.88000
245.76000
245.76000
245.76000
245.76000
TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
Table A-4. Reference Clock Selection – CPRI Mode
Jitter Cleaner
Multiplier
OFF
0.25
0.5
1
2
OFF
0.25
0.5
1
2
OFF
0.25
0.5
1
Legal Clocking Mode – CPRI Mode Settings
SERDES
REFCLK Input
(MHz)
SERDES PLL
Multiplier
Serial Data Rate = f(SPEED[1:0]) (Mbps)
Full (00)
Half (01)
Qrtr. (10)
61.44000
20
2457.600
1228.800
614.400
15.36000
30.72000
61.44000
20
2457.600
1228.800
614.400
122.88000
10
2457.600
1228.800
614.400
122.88000
10
2457.600
1228.800
614.400
30.72000
61.44000
20
2457.600
1228.800
614.400
122.88000
10
2457.600
1228.800
614.400
245.76000
5
2457.600
1228.800
614.400
245.76000
5
2457.600
1228.800
614.400
61.44000
20
2457.600
1228.800
614.400
122.88000
10
2457.600
1228.800
614.400
245.76000
5
2457.600
1228.800
614.400
Table A-5. Reference Clock Selection – 9/10 Bit SERDES Mode – Full Rate (SPEED[1:0] = 00)
Nine/Ten Bit SERDES Mode – Clock Range Support (RATE[1:0]=00) (Full)
REFCLK
Minimum
(MHz)
Maximum
(MHz)
Jitter Cleaner
Multiplier
SERDES REFCLK
Minimum
(MHz)
Maximum
(MHz)
SERDES PLL
Multiplier
Serial Data Rate (Mbps)
FULL
Minimum
Maximum
200.0000
375.0000
OFF
200.0000
375.0000
5
2000.00
3750.00
100.0000
187.5000
OFF
100.0000
187.5000
10
2000.00
3750.00
50.0000
93.7500
OFF
50.0000
93.7500
20
2000.00
3750.00
0.25
5
0.25
10
200.0000
375.0000
0.25
50.0000
93.7500
20
2000.00
3750.00
0.5
5
200.0000
375.0000
0.5
100.0000
187.5000
10
2000.00
3750.00
100.0000
187.5000
0.5
50.0000
93.7500
20
2000.00
3750.00
1
5
100.0000
187.5000
1
100.0000
187.5000
10
2000.00
3750.00
50.0000
93.7500
1
50.0000
93.7500
20
2000.00
3750.00
2
5
50.0000
93.7500
2
100.0000
187.5000
10
2000.00
3750.00
2
20
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APPENDIX A – Frequency Ranges Supported
89