TLK3132 Datasheet, PDF (50/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
BIT(s)
37632.7:6
37632.3:2
Table 2-72. HSTL_INPUT_TERMINATION_CONTROL
ADDRESS: 0x9300
NAME
HSTL_TERM_1[1:0]
HSTL_TERM_0[1:0]
DEFAULT: 0x0000
DESCRIPTION
Termination setting for input HSTL cells (for CH 1)
00 = Termination disable (High Impedance)
01 = Half termination strength (300 Ω to VHSTL and GND)
10 = 3/4 termination strength (200 Ω to VHSTL&GND)
11 = Full termination strength (150 Ω to VHSTL&GND)
Termination setting for input HSTL cells (for CH 0)
00 = Termination disable (High Impedance)
01 = Half termination strength (300 Ω to VHSTL&GND)
10 = 3/4 termination strength (200 Ω to VHSTL&GND)
11 = Full termination strength (150 Ω to VHSTL&GND)
www.ti.com
ACCESS
RW
RW
BIT(s)
37633.7:6
37633.3:2
Table 2-73. HSTL_OUTPUT_SLEWRATE_CONTROL
ADDRESS: 0x9301
DEFAULT: 0x0000
NAME
DESCRIPTION
HSTL_SLEW_RATE_1
[1:0]
Slew Rate setting for output HSTL cells (for CH 1)
00 = No slew control (fastest edge)
01 = 33% slew control
10 = 66% slew control termination strength
11 = Full slew control (slowest edge)
HSTL_SLEW_RATE_0
[1:0]
Slew Rate setting for output HSTL cells (for CH 0)
00 = No slew control (fastest edge)
01 = 33% slew control
10 = 66% slew control termination strength
11 = Full slew control (slowest edge)
ACCESS
RW
RW
BIT(s)
37634.15
37634.14
37634.13
37634.12
37634.11:9
37634.7:5
37634.3
Table 2-74. HSTL_INPUT_VTP_CONTROL
ADDRESS: 0x9302
DEFAULT: 0x0640
NAME
DESCRIPTION
I_FORCE_UP_N
When set, increases NFET strength in all HSTL input cells. For TI purposes Only
I_FORCE_UP_P
When set, increases PFET strength in all HSTL input cells. For TI purposes Only
I_FORCE_DOWN_N
When set, decreases NFET strength in all HSTL input cells. For TI purposes
Only
I_FORCE_DOWN_P
When set, decreases PFET strength in all HSTL input cells. For TI purposes
Only
I_VTP_DRIVE[2:0]
Drive strength control for HSTL input cells
3’b000 = 30% drive strength increase
3’b001 = 20% drive strength increase
3’b010 = 10% drive strength increase
3’b011 = Normal drive strength (default)
3’b100 = 10% drive strength decrease
3’b101 = 20% drive strength decrease
3’b110 = 30% drive strength decrease
3’b111 = 40% drive strength decrease
I_FILTER_CONTROL[2:0]
Filter Control
3’b000 = Impedance change filtering off
3’b001 = Update on 2 consecutive update requests
3’b010 = Update on 3 consecutive update requests(default)
3’b011 = Update on 4 consecutive update requests
3’b100 = Update on 5 consecutive update requests
3’b101 = Update on 6 consecutive update requests
3’b110 = Update on 7 consecutive update requests
3’b111 = Update on 8 consecutive update requests
I_LOCK
Impedance Lock Control
When set, disables dynamic impedance control updates for HSTL input cells
ACCESS
RW
RW
RW
RW
50
Detailed Description
Submit Documentation Feedback