TLK3132 Datasheet, PDF (70/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
RECOMMENDED OPERATING CONDITIONS (continued)
AVDD, VDDD, VDDT (1.26V)
DVDD (1.26V)
I_SD ⁽¹⁾
Shutdown
current
VDDR (1.9V)
VDDQ (1.9V)
VDDO (2.63V)
VDDA_VCO, VDD_PLL, VDD_CML, VDDA_CP
(1.26V)
(1) Toggle RST_N before setting ENABLE low for proper shutdown.
ENABLE low
ENABLE low, HSTL powerdown
ENABLE low
ENABLE low, HSTL powerdown
ENABLE low
ENABLE low, HSTL powerdown
ENABLE low
ENABLE low, HSTL powerdown
ENABLE low
ENABLE low, HSTL powerdown
ENABLE low
ENABLE low, HSTL powerdown
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MIN NOM MAX UNIT
25
mA
25
61
mA
21
1
mA
1
140
mA
10
17
mA
17
1
mA
1
4.3 REFERENCE CLOCK TIMING REQUIREMENTS (REFCLKP/N)⁽¹⁾
PARAMETER
Frequency
Accuracy
Accuracy to TXCLK
Duty Cycle
Jitter
Minimum data rate
1G PCS Mode
All
CONDITION
Random and deterministic
MIN
60
–100
0
45%
NOM
–
0
50%
MAX
375
100
0
55%
40
UNIT
MHz
ppm
ppm
ps
(1) This clock should be crystal referenced to meet the requirements of the above table. Contact TI for specific clocking recommendations.
4.4 REFERENCE CLOCK ELECTRICAL CHARACTERISTICS (REFCLKP/N)
PARAMETER
V_id
Differential Input Voltage
C_IN
Input Capacitance
R_IN
Input Differential Impedance
t_rise
Rise Time
20% to 80%
CONDITION
MIN NOM
100
80 100
50
MAX
2000
3
120
600
UNIT
mV_PP
pF
Ω
ps
4.5 SINGLE ENDED REFERENCE CLOCK ELECTRICAL CHARACTERISTICS (REFCLK)
V_IH
V_IL
I_IH/I_IL
t_rise
Jitter
T_cyc
PARAMETER
High-Level Input Voltage
Low-Level Input Voltage
High/Low Input Current
Rise Time
Peak to Peak Jitter
Duty Cycle
CONDITION
20% → 80%
Jitter Cleaner not used on REFCLK
MIN
1.7
–0.3
40%
NOM
MAX
VDDO + 0.3
0.7
±10
1
40
50%
60%
UNIT
V
V
µA
ns
ps
Period
70
Electrical Specifications
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