TLK3132 Datasheet, PDF (93/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
9/10 Bit SERDES Mode - Continuous Mode - Jitter Cleaner (2x) Mode
SERDES RATE [1:0] (See Note 2 Below)
REFCLK (Mhz)
REF_DIV[6:0] FB_DIV[6:0]
4/5.37124:14:8 4/5.37124:6:0 PLL_MULT[3:0] RXTX_DIV[6:0]
2'b00 (Full)
2'b01 (Half)
2'b10 (Quarter)
Min
Max
(Decimal)
(Decimal) See Note 1 Below 4/5.37125:6:0
Min
Max
Min
Max
Min
Max
50.0000 52.0833
1
60
10
30
2000.000 2083.333 1000.000 1041.667 500.000 520.833
50.4310 53.8793
1
58
10
29
2017.241 2155.172 1008.621 1077.586 504.310 538.793
52.2321 55.8036
1
56
10
28
2089.286 2232.143 1044.643 1116.071 522.321 558.036
54.1667 57.8704
1
54
10
27
2166.667 2314.815 1083.333 1157.407 541.667 578.704
56.2500 60.0962
1
52
10
26
2250.000 2403.846 1125.000 1201.923 562.500 600.962
58.5000 62.5000
1
50
10
25
2340.000 2500.000 1170.000 1250.000 600.000 625.000
60.9375 65.1042
1
48
10
24
2437.500 2604.167 1218.750 1302.083 609.375 651.042
63.5870 67.9348
1
46
10
23
2543.478 2717.391 1271.739 1358.696 635.870 679.348
66.4773 71.0227
1
44
10
22
2659.091 2840.909 1329.545 1420.455 664.773 710.227
69.6429 74.4048
1
42
10
21
2785.714 2976.190 1392.857 1488.095 696.429 744.048
73.1250 78.1250
1
40
10
20
2925.000 3125.000 1462.500 1562.500 731.250 781.250
76.9737 82.2368
1
38
10
19
3078.947 3289.474 1539.474 1644.737 769.737 822.368
81.2500 86.8056
1
36
10
18
3250.000 3472.222 1625.000 1736.111 812.500 868.056
86.0294 91.9118
1
34
10
17
3441.176 3676.471 1720.588 1838.235 860.294 919.118
91.4063 97.6563
1
32
10
16
3656.250 3750.000 1828.125 1953.125 914.063 976.563
97.5000 100.0000
1
30
10
15
3900.000 4000.000 1950.000 2000.000 975.000 1000.000
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
Note that REFCLK is limited to 93.75 MHz when in full rate mode to achieve 3750 Mbps serial data rate.
Figure A-2. 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (2x) Provisioning
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APPENDIX A – Frequency Ranges Supported
93