TLK3132 Datasheet, PDF (76/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
www.ti.com
Table 4-2. Parallel Interface – Valid Signal Operational Mode Definitions
TIMING
MODE
NAME
USAGE MODE
RGMII, RTBI
1000Base-X Applications, Reduced Ten Bit Applications (RTBI)
Only DDR Timing Supported
See Section 4.11: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.13: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In RGMII Mode
CH0: TX_EN/TX_ER = TXD_[4]
CH1: TX_EN/TX_ER = TXD_[12]
CH0: RX_DV/RX_ER = RXD_[4]
CH1: RX_EN/RX_ER = RXD_[12]
TBI, GMII
Ten Bit Interface Mode (TBI)
Only SDR Timing Supported
See Section 4.12: HSTL Output Switching Characteristics (SDR Timing
Mode Only) and Section 4.14: HSTL (SDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In GMII Mode
CH0: TX_EN = TXC_[0]
CH1: TX_EN = TXC_[1]
CH0: TX_ER = TXC_[4]
CH1: TX_ER = TXC_[5]
CH0: RX_DV = RXC_[0]
CH1: TX_DV = RXC_[1]
CH0: RX_ER = RXC_[4]
CH1: RX_ER = RXC_[5]
Note: In TBI Mode
CH0: TX Data Bit 8 = TXC_[0]
CH1: TX Data Bit 8 = TXC_[1]
CH0: TX Data Bit 9 = TXC_[4]
CH1: TX Data Bit 9 = TXC_[5]
CH0: RX Data Bit 8 = RXC_[0]
CH1: RX Data Bit 8 = RXC_[1]
CH0: RX Data Bit 9 = RXC_[4]
CH1: RX Data Bit 9 = RXC_[5]
Eight Bit Interface Mode (EBI)
SDR Timing Support
EBI
See Section 4.12: HSTL Output Switching Characteristics (SDR Timing
Mode Only) and Section 4.14: HSTL (SDR Timing Mode Only) Input Timing
Requirements for AC timing details.
REBI
Reduced Eight Bit Interface Mode (REBI)
DDR Timing Support
See Section 4.11: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.13: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Nine Bit Interface Mode (NBI)
(Un-encoded Data Byte + 1 Control Bit)
SDR Timing Support
See Section 4.12: HSTL Output Switching Characteristics (SDR Timing
Mode Only) and Section 4.14: HSTL (SDR Timing Mode Only) Input Timing
NBI
Requirements for AC timing details.
Note: In NBI Mode
CH0: TX Control Bit = TXC_[0]
CH1: TX Control Bit = TXC_[1]
CH0: RX Control Bit = RXC_[0]
CH1: RX Control Bit = RXC_[1]
RNBI
Reduced Nine Bit Interface Mode (RNBI)
(Un-encoded Data Byte + 1 Control Bit)
DDR Timing Support
See Section 4.11: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.13: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In RNBI Mode
CH0: TX Control Bit = TXD_[4]
CH1: TX Control Bit = TXD_[12]
CH0: RX Control Bit = RXD_[4]
CH1: RX Control Bit = RXD_[12]
TBID
Ten Bit Interface DDR Mode (TBID)
Only DDR Timing Supported
See Section 4.11: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.13: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In TBID Mode
CH0: TX Data Bit 8 = TXC_[0]
CH1: TX Data Bit 8 = TXC_[1]
CH0: TX Data Bit 9 = TXC_[4]
CH1: TX Data Bit 9 = TXC_[5]
CH0: RX Data Bit 8 = RXC_[0]
CH1: RX Data Bit 8 = RXC_[1]
CH0: TX Data Bit 9 = RXC_[4]
CH1: TX Data Bit 9 = RXC_[5]
TX SIGNALS USED
TXDATA = TXD_[4:0]
TXCLK = TXCLK_[0]
-OR-
TXDATA = TXD_[12:8]
TXCLK = TXCLK_[1]
TXDATA = TXC_ [4],TXC_ [0],
TXD[7:0]
TXCLK = TXCLK_ [0]
-OR-
TXDATA = TXC_ [5],TXC_ [1],
TXD[15:8]
TXCLK = TXCLK_ [1]
TXDATA = TXD_ [7:0]
TXCLK = TXCLK_ [0]
-OR-
TXDATA = TXD_ [15:8]
TXCLK = TXCLK_ [1]
TXDATA = TXD_ [3:0]
TXCLK = TXCLK_ [0]
-OR-
TXDATA = TXD_ [11:8]
TXCLK = TXCLK_ [1]
TXDATA = TXC_ [0], TXD[7:0]
TXCLK = TXCLK_ [0]
-OR-
TXDATA = TXC_ [1], TXD[15:8]
TXCLK = TXCLK_ [1]
TXDATA = TXD_[4:0]
TXCLK = TXCLK_[0]
-OR-
TXDATA = TXD_[12:8]
TXCLK = TXCLK_[1]
TXDATA = TXC_ [4],TXC_ [0],
TXD[7:0]
TXCLK = TXCLK_ [0]
-OR-
TXDATA = TXC_ [5],TXC_ [1],
TXD[15:8]
TXCLK = TXCLK_ [1]
RX SIGNALS USED
RXDATA = RXD_[4:0]
RXCLK = RXCLK_[0]
-OR-
RXDATA = RXD_[12:8]
RXCLK = RXCLK_[1]
RXDATA = RXC_ [4],RXC_ [0],
RXD[7:0]
RXCLK = RXCLK_ [0]
-OR-
RXDATA = RXC_ [5],RXC_ [1],
RXD[15:8]
RXCLK = RXCLK_ [1]
RXDATA = RXD_ [7:0]
RXCLK = RXCLK_ [0]
-OR-
RXDATA = RXD_ [15:8]
RXCLK = RXCLK_ [1]
RXDATA = RXD_ [3:0]
RXCLK = RXCLK_ [0]
-OR-
RXDATA = RXD_ [11:8]
RXCLK = RXCLK_ [1]
RXDATA = RXC_ [0], RXD[7:0]
RXCLK = RXCLK_ [0]
-OR-
RXDATA = RXC_ [1], RXD[15:8]
RXCLK = RXCLK_ [1]
RXDATA = RXD_[4:0]
RXCLK = RXCLK_[0]
-OR-
RXDATA = RXD_[12:8]
RXCLK = RXCLK_[1]
RXDATA = RXC_ [4],RXC_ [0],
RXD[7:0]
RXCLK = RXCLK_ [0]
OR
RXDATA = RXC_ [5],RXC_ [1],
RXD[15:8]
RXCLK = RXCLK_ [1]
76
Electrical Specifications
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