TLK3132 Datasheet, PDF (19/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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2.7.2 RTBI Mode (Reduced Ten Bit Interface)
TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
DATA CHANNEL
NUMBER
Channel 0
Channel 1
Table 2-4. RTBI – Lane To Functional Pin Mapping
TRANSMIT DATA 5 BITS
(INPUT)
TXD_[4:0]
TXD_[12:8]
RECEIVE DATA 5 BITS
(OUTPUT)
RXD_[4:0]
RXD_[12:8]
TRANSMIT CLOCK
(INPUT)
TXCLK_[0]
TXCLK_[1]
RECEIVE CLOCK
(OUTPUT)
RXCLK_[0]
RXCLK_[1]
TXCLK_[0]
DDR Source Centered Timing
(Nibble Order = 1 Default)
TXD_[4:0]
Data0[4:0]
Data0[9:5]
DDR Source Centered Timing
(Nibble Order = 0)
TXCLK_[0]
TXD_[4:0]
Data0[9:5]
Data0[4:0]
RXCLK_[0]
RXD_[4:0]
Data0[4:0]
Data0[9:5]
TXCLK_[0]
DDR Source Aligned Timing
(Nibble Order = 1 Default)
TXD_[4:0]
Data0[4:0]
Data0[9:5]
RXCLK_[0]
RXD_[4:0]
Data0[9:5]
Data0[4:0]
DDR Source Aligned Timing
(Nibble Order = 0)
TXCLK_[0]
TXD_[4:0]
Data0[9:5]
Data0[4:0]
RXCLK_[0]
RXD_[4:0]
Data0[4:0]
Data0[9:5]
RXCLK_[0]
RXD_[4:0]
Data0[9:5]
Data0[4:0]
Figure 2-9. RTBI – Individual Channel Byte Ordering – Channel 0 Example
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