TLK3132 Datasheet, PDF (65/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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SIGNAL
TXCLK_[1:0]
TXD_[15:0]
LOCATION
D10
G12
B8
C9
A8
B10
A12
A13
B12
A14
B14
D11
E12
F11
C11
F12
D12
C12
B9
TXC_[5,4,1,0]
D9
D13
C14
RXCLK_[1:0]
B5
A6
E4
E3
D4
E2
D3
E1
C1
RXD_[15:0]
D2
B1
C3
D6
C2
B2
C7
A4
A2
C4
RXC_[5,4,1,0]
A5
C6
D7
VOLTAGE
VDDQ/
VREF1/2
VDDQ/
VREF1/2
TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
Table 3-4. Parallel Data Pins
TYPE
DESCRIPTION
1.5/1.8 V Transmit Data Clock (Parallel I/F) These two signals are the parallel side
HSTL Input input clocks per channel.
1.5/1.8 V
HSTL Input
Transmit Data Pins Parallel interface data pins.
See the following tables for functionality per application mode:
Table 2-3 RGMII - Lane To Functional Pin Mapping
Table 2-4 RTBI - Lane To Functional Pin Mapping
Table 2-5 TBI - Lane To Functional Pin Mapping
Table 2-6 GMII - Lane To Functional Pin Mapping
Table 2-7 EBI - Lane To Functional Pin Mapping
Table 2-8 REBI - Lane To Functional Pin Mapping
Table 2-9 NBI - Lane To Functional Pin Mapping
Table 2-10 RNBI - Lane To Functional Pin Mapping
Table 2-11 TBID - Lane To Functional Pin Mapping
Table 2-12 NBID - Lane To Functional Pin Mapping
VDDQ/
VREF1/2
VDDQ
VDDQ
1.5/1.8 V
HSTL Input
Transmit Data Control Parallel Control inputs.
See the following tables for functionality per application mode:
Table 2-3 RGMII - Lane To Functional Pin Mapping
Table 2-4 RTBI - Lane To Functional Pin Mapping
Table 2-5 TBI - Lane To Functional Pin Mapping
Table 2-6 GMII - Lane To Functional Pin Mapping
Table 2-7 EBI - Lane To Functional Pin Mapping
Table 2-8 REBI - Lane To Functional Pin Mapping
Table 2-9 NBI - Lane To Functional Pin Mapping
Table 2-10 RNBI - Lane To Functional Pin Mapping
Table 2-11 TBID - Lane To Functional Pin Mapping
Table 2-12 NBID - Lane To Functional Pin Mapping
1.5/1.8 V
HSTL
Output
Receive Data Clock These two signals are the parallel side output clocks
per channel.
1.5/1.8 V
HSTL
Output
Receive Data Pins Parallel interface data pins.
See the following tables for functionality per application mode:
Table 2-3 RGMII - Lane To Functional Pin Mapping
Table 2-4 RTBI - Lane To Functional Pin Mapping
Table 2-5 TBI - Lane To Functional Pin Mapping
Table 2-6 GMII - Lane To Functional Pin Mapping
Table 2-7 EBI - Lane To Functional Pin Mapping
Table 2-8 REBI - Lane To Functional Pin Mapping
Table 2-9 NBI - Lane To Functional Pin Mapping
Table 2-10 RNBI - Lane To Functional Pin Mapping
Table 2-11 TBID - Lane To Functional Pin Mapping
Table 2-12 NBID - Lane To Functional Pin Mapping
VDDQ
1.5/1.8 V
HSTL
Output
Receive Data Control Control inputs.
See the following tables for functionality per application mode:
Table 2-3 RGMII - Lane To Functional Pin Mapping
Table 2-4 RTBI - Lane To Functional Pin Mapping
Table 2-5 TBI - Lane To Functional Pin Mapping
Table 2-6 GMII - Lane To Functional Pin Mapping
Table 2-7 EBI - Lane To Functional Pin Mapping
Table 2-8 REBI - Lane To Functional Pin Mapping
Table 2-9 NBI - Lane To Functional Pin Mapping
Table 2-10 RNBI - Lane To Functional Pin Mapping
Table 2-11 TBID - Lane To Functional Pin Mapping
Table 2-12 NBID - Lane To Functional Pin Mapping
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Device Reset Requirements/Procedure
65