TLK3132 Datasheet, PDF (6/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
www.ti.com
List of Tables
2-1 Supported Protocol Rates and REFCLK Values.............................................................................. 12
2-2 Device Operation Modes......................................................................................................... 17
2-3 RGMII – Lane To Functional Pin Mapping..................................................................................... 18
2-4 RTBI – Lane To Functional Pin Mapping ...................................................................................... 19
2-5 TBI – Lane To Functional Pin Mapping ........................................................................................ 20
2-6 GMII – Lane To Functional Pin Mapping....................................................................................... 21
2-7 EBI – Lane To Functional Pin Mapping ........................................................................................ 22
2-8 REBI – Lane To Functional Pin Mapping ...................................................................................... 23
2-9 NBI – Lane To Functional Pin Mapping ........................................................................................ 24
2-10 RNBI – Lane To Functional Pin Mapping ...................................................................................... 25
2-11 TBID – Lane To Functional Pin Mapping ...................................................................................... 26
2-12 NBID – Lane To Functional Pin Mapping ...................................................................................... 27
2-13 PHY_CONTROL_1 ............................................................................................................... 34
2-14 PHY_STATUS_1 .................................................................................................................. 34
2-15 PHY_IDENTIFIER_1.............................................................................................................. 35
2-16 PHY_IDENTIFIER_2.............................................................................................................. 35
2-17 PHY_EXT_STATUS .............................................................................................................. 35
2-18 PHY_CH_CONTROL_1 .......................................................................................................... 35
2-19 PHY_CH_CONTROL_2 .......................................................................................................... 36
2-20 PHY_RX_CTC_FIFO_STATUS ................................................................................................. 37
2-21 PHY_TX_CTC_FIFO_STATUS ................................................................................................. 37
2-22 PHY_TX_WIDE_FIFO _STATUS ............................................................................................... 37
2-23 PHY_TEST_PATTERN_SYNC_STATUS ..................................................................................... 37
2-24 PHY_TEST_PATTERN_COUNTER............................................................................................ 38
2-25 PHY_CRPAT_PATTERN_COUNTER_1 ...................................................................................... 38
2-26 PHY_CRPAT_PATTERN_COUNTER_2 ...................................................................................... 38
2-27 PHY_TEST_MODE_CONTROL ................................................................................................ 38
2-28 PHY_CHANNEL_STATUS....................................................................................................... 38
2-29 PHY_PRBS_HIGH_SPEED_TEST_COUNTER .............................................................................. 38
2-30 PHY_EXT_ADDRESS_CONTROL ............................................................................................. 39
2-31 PHY_EXT_ADDRESS_DATA ................................................................................................... 39
2-32 SERDES_PLL_CONFIG ......................................................................................................... 39
2-33 PLL Multiplier Control............................................................................................................. 39
2-34 SERDES_RATE_CONFIG_TX_RX............................................................................................. 40
2-35 SERDES_RX0_CONFIG......................................................................................................... 40
2-36 SERDES_RX1_CONFIG......................................................................................................... 41
2-37 SERDES_TX0_CONFIG ......................................................................................................... 41
2-38 SERDES_TX1_CONFIG ......................................................................................................... 42
2-39 Transmit De-Emphasis Control.................................................................................................. 42
6
List of Tables
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