TLK3132 Datasheet, PDF (44/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
Table 2-43. SERDES_RX0_STATUS⁽¹⁾
ADDRESS: 0x9013
DEFAULT: 0x0000
BIT(s)
NAME
DESCRIPTION
36883.3 LOSDTCT
When HIGH indicates Loss of Signal condition is detected for RX CH 0
36883.2 ODDCG
LOW when SYNC is HIGH. After that toggles every cycle.
36883.1 SYNC
When comma detection is enabled, this bit is HIGH when an aligned comma is
received.
36883.0
RX CH 0 TESTFAIL
When HIGH, indicates an error occurred during test pattern verification for SERDES
RX CH 0.
This bit status is valid only when SERDES RX test pattern verification bits are set.
(1) Above status bits are only for Receive CH 0.
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ACCESS
RO
RO
RO
RO
Table 2-44. SERDES_RX1_STATUS⁽¹⁾
BIT(s)
36884.3
36884.2
36884.1
36884.0
ADDRESS: 0x9014
DEFAULT: 0x0000
NAME
DESCRIPTION
LOSDTCT
When HIGH indicates Loss of Signal condition is detected for RX CH 1
ODDCG
LOW when SYNC is HIGH. After that toggles every cycle.
SYNC
When comma detection is enabled, this bit is HIGH when an aligned comma is
received.
When HIGH, indicates an error occurred during test pattern verification for SERDES
RX CH 1 TESTFAIL RX CH 1.
This bit status is valid only when SERDES RX test pattern verification bits are set.
(1) Above status bits are only for Receive CH 1
ACCESS
RO
RO
RO
RO
Table 2-45. SERDES_TX0_STATUS⁽¹⁾
BIT(s)
36887.0
ADDRESS: 0x9017
DEFAULT: 0x0000
NAME
DESCRIPTION
TX CH 0 TESTFAIL
When HIGH, indicates an error occurred during test pattern verification for SERDES
TX CH 0.
(1) Above status bits are only for Transmit CH 0.
ACCESS
RO
Table 2-46. SERDES_TX1_STATUS⁽¹⁾
BIT(s)
36888.0
ADDRESS: 0x9018
DEFAULT: 0x0000
NAME
DESCRIPTION
TX CH 1 TESTFAIL
When HIGH, indicates an error occurred during test pattern verification for SERDES
TX CH 1.
(1) Above status bits are only for Transmit CH 1.
ACCESS
RO
BIT(s)
36891.4
36891.0
Table 2-47. SERDES_PLL_STATUS
ADDRESS: 0x901B
DEFAULT: 0x0000
NAME
DESCRIPTION
PLL_LOCK_RX
1 = Indicates PLL is locked within 10ppm of REFCLKP/N in SERDES RX macro
PLL_LOCK_TX
1 = Indicates PLL is locked within 10ppm of REFCLKP/N in SERDES TX macro
ACCESS
RO/LL
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Detailed Description
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