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TLK3132 Datasheet, PDF (36/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver | |||
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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 â DECEMBER 2008
BIT(s)
16.7
16.6
16.5
16.4
16.3
16.2:0
Table 2-18. PHY_CH_CONTROL_1 (continued)
ADDRESS: 0x10
DEFAULT: 0x0000
NAME
DESCRIPTION
PRBS Verifier Enable
A logic 1 enables the PRBS (2^7) verifier in the receive datapath.
Logically ORed with the PRBSEN pin. (Default 1âb0)
PRBS Generator Enable
A logic 1 enables the PRBS (2^7) generator in the transmit datapath. Logically
ORed with the PRBSEN pin. (Default 1âb0)
Channel sync freeze control When set, freezes last acquired word alignment. (Default 1âb0)
Test Pattern Generator Enable When high activates the generator selected by bits 16.2:0. (Default 1âb0)
Test Pattern Verifier Enable When high activates the verifier selected by bits 16.2:0. (Default 1âb0)
Pattern Select
Test Pattern Selection
000 = High Frequency Test Pattern (Default 3âb000)
001 = Low Frequency Test Pattern
010 = Mixed Frequency Test Pattern
011 = CRPAT Long
100 = CRPAT Short
Others = Reserved
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ACCESS
RW
RW
RW
RW
RW
RW
BIT(s)
17.15
17.14
17.13
17.12
17.11
17.10
17.9
17.8
17.7
17.6
17.5
17.4
Table 2-19. PHY_CH_CONTROL_2
ADDRESS: 0x11
DEFAULT: 0x3590
NAME
DESCRIPTION
Global write
When written as 1 the settings in 17.14:0 will affect all channels of one device
simultaneously.
When written as 0 the settings in 17.14:0 are only valid for the addressed channel.
This value always reads zero.
Sync Status Override
1 = Causes an override of the sync state of 1000Base-X synchronization state
machine to reflect a â1â in the sync_status (1.2) bit.
0 = Original (normal operation) sync_status value is represented in bit 1.2. (Default
1âb0)
TX PMA Bit Order
When asserted, allows the ten bits of data given to the parallel side of the
SERDES TX macro to be flipped. This is normally set since the SERDES transmits
MSB first, and the 1000Base-X standard requires LSB to be transmitted first. For
standard based operation, the customer may leave this bit alone. (Default 1âb1)
RX PMA Bit Order
When asserted, allows the ten bits of data received from the parallel side of the
SERDES RX macro to be flipped. This is normally set since the SERDES receives
MSB first, and the 1000Base-X standard requires LSB to be received first. For
standard based operation, the customer may leave this bit alone. (Default 1âb1)
LOS Override
1 = Overrides Loss of signal (LOS) status coming from SERDES. Synchronization
turned on irrespective of LOS status
0 = Synchronization depends on LOS status. (Default 1âb0)
CTC enable
1 = Clock Tolerance Compensation on receive datapath is enabled (Default 1âb1)
0 = Clock Tolerance Compensation on receive datapath is disabled
Full DDR mode
1 = Sets the device in full DDR mode (NBID/TBID modes)
0 = Disables full DDR mode (Default)
RCLK out enable
1 = Enables RX_CLK out (Default 1âb1)
0 = Disables RX_CLK out.
RX_CLK will be low when this bit is de-asserted
Comma enable
1 = Enables comma detection (Default 1âb1)
0 = Disables comma detection
FC enable
1 = Enables FC_PH overlay detection. This is needed in 1x/2x Fiber channel mode
to allow proper detection of EOF 8B/10B disparity
0 = Disables FC_PH overlay detection (Default 1âb0)
Data mode
Valid only when 17.9 (Full DDR mode) is LOW.
1 = Enables DDR data mode on parallel Transmit and Receive directions (data
clocked on both rising and falling edge)
0 = Enables SDR data mode on parallel Transmit and Receive directions (data is
clocked only on rising edge or only on falling edge) (Default 1âb0)
Nibble order
Applicable only in non FULL DDR modes
1 = LSB on rising edge followed by MSB on falling edge (Default 1âb1)
0 = MSB on rising edge followed by LSB on falling edge
ACCESS
RW/SC
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
36
Detailed Description
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