TLK3132 Datasheet, PDF (43/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

www.ti.com
TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
Table 2-41. SERDES_TEST_CONFIG_TX⁽¹⁾
ADDRESS: 0x9011
DEFAULT: 0x0000
BIT(s)
NAME
DESCRIPTION
36881.10:8
Reserved
Reserved for TI test.
36881.7:6
LOOPBACK_TX
00 = Disabled
01 = Pad loopback. For TI purposes only
10 = Inner loopback (CML driver disabled)
11 = Inner loopback (CML driver enabled)
36881.5:4
CLKBYPASS_TX
PLL Bypass control in test mode
00 = No bypass
01 = Reserved
10 = Functional bypass. Macros run using TESCLKT
11 = Refclk observe (Reserved. For TI purposes only)
36881.3
ENRXPATT_TX
0 – Disables test pattern verification in SERDES TX macro.
1 – Enables test pattern verification in SERDES TX macro.
36881.2
ENTXPATT_TX
0 – Disables test pattern generation in SERDES TX macro.
1 – Enables test pattern generation in SERDES TX macro.
36881.1:0
TESTPATT_TX
Valid when ENTXPATT_TX, ENRXPATT_TX, ENTEST_TX are set
00 = Reserved (Default)
01 = Clock pattern (Half baud clock pattern with period of 2UI)
10 = 2⁷ – 1 PRBS pattern
11 = 2²³ – 1 PRBS pattern
(1) Above control bits are only for vendor testing only. Customer should leave them at their default values.
ACCESS
RW
RW
RW
RW
RW
RW
Table 2-42. SERDES_TEST_CONFIG_RX⁽¹⁾
BIT(s)
36882.10:8
36882.7:6
36882.5:4
36882.3
36882.2
36882.1:0
ADDRESS: 0x9012
DEFAULT: 0x0000
NAME
DESCRIPTION
Reserved
Reserved for TI test.
LOOPBACK_RX
00 = Disabled
01 = Pad loopback. For TI purposes only
10 = Inner loopback (CML driver disabled)
11 = Inner loopback (CML driver enabled)
CLKBYPASS_RX
PLL Bypass control in test mode
00 = No bypass
01 = Reserved
10 = Functional bypass. Macros run using TESCLKR
11 = Refclk observe (Reserved. For TI purposes only)
ENRXPATT_RX
0 – Disables test pattern verification in SERDES RX macro.
1 – Enables test pattern verification in SERDES RX macro.
ENTXPATT_RX
0 – Disables test pattern generation in SERDES RX macro.
1 – Enables test pattern generation in SERDES RX macro.
TESTPATT_RX
Valid when ENTXPATT_RX, ENRXPATT_RX, ENTEST_RX are set
00 = Reserved (Default)
01 = Clock pattern (Half baud clock pattern with period of 2UI)
10 = 2⁷ – 1 PRBS pattern
11 = 2²³ – 1 PRBS pattern
(1) Above control bits are only for vendor testing only. Customer should leave them at their default values
ACCESS
RW
RW
RW
RW
RW
RW
Submit Documentation Feedback
Detailed Description
43