TLK3132 Datasheet, PDF (79/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
4.12 HSTL Output Switching Characteristics (SDR Timing Mode Only)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
T_duty
t_period
T_freq
T_pd
T_pd
RXCLK Duty Cycle
RXCLK Period
RXCLK Frequency
RXCLK rising to RXDATA
valid
RXCLK falling to RXDATA
valid
TEST CONDITIONS
Rising and Falling Edge Aligned Data
Note: C_load = 10pF, using timing reference of VDDQ/2
Rising and Falling Edge Aligned Data
Rising and Falling Edge Aligned Data
Rising Edge Aligned, See Figure 4-7
Note: C_load = 10pF, using timing reference of VDDQ/2.
Falling Edge Aligned, See Figure 4-8
Note: C_load = 10pF, using timing reference of VDDQ/2.
MIN
MAX UNIT
40%
60%
2.67
16.67 ns
60
375 MHz
–0.10 × t_period +0.10 × t_period ps
–0.10 × t_period +0.10 × t_period ps
RXCLK
t_PERIOD
V_OH(ac)
VDDQ/2
V_OL(ac)
T_PD
V_OH(ac)
RXDATA VDDQ/2
V_OL(ac)
Figure 4-7. HSTL (SDR Timing Mode Only) Rising Edge Aligned Output Timing Requirements
RXCLK
t_PERIOD
T_PD
V_OH(ac)
RXDATA VDDQ/2
V_OL(ac)
V_OH(ac)
VDDQ/2
V_OL(ac)
Figure 4-8. HSTL (SDR Timing Mode Only) Falling Edge Aligned Output Timing Requirements
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Electrical Specifications
79