TLK3132 Datasheet, PDF (75/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
+100
0
-100
0.325
0.675
1.0
Unit Interval
Figure 4-3. Receive Template
J_DR
J_R
J_R
J_TOL
Note: J_TOL = J_R + J_DR, where J_TOL is the receive jitter tolerance, J_DR is the received deterministic jitter, and J_R is the
Gaussian random edge jitter distribution at a maximum BER = 10^-12.
Figure 4-4. Input Jitter
The TLK3132 has several different application modes, which impact parallel interface I/O timing definitions. Each
of the modes is defined below, and then subsequently referred to in the detailed timing parameter definitions.
RXDATA and RXCLK, and TXDATA and TXCLK in the detailed timing specification will be defined by the exact
following signal definitions.
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Electrical Specifications
75