TLK3132 Datasheet, PDF (80/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
www.ti.com
4.13 HSTL (DDR Timing Mode Only) Input Timing Requirements
over operating free-air temperature range (unless otherwise noted)
t_setup
t_hold
t_duty
t_duty
t_period
T_freq
T_skew
PARAMETER
TEST CONDITIONS
TXDATA setup prior to
TXCLK transition high or
low
Source Centered. See Figure 4-9.
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all input signals.
TXDATA hold after TXCLK
transition high or low
Source Centered. See Figure 4-9.
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all input signals.
TXCLK Duty Cycle
Source Centered
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all input signals.
TXCLK Duty Cycle
Source Aligned
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all input signals.
TXCLK Period
Source Centered and Aligned.
TXCLK Frequency
Source Centered and Aligned.
TXCLK rising or falling to
TXDATA valid.
Source Aligned. See Figure 4-10.
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all inputs signals.
MIN NOM⁽¹⁾
0.075 × t_period
0.075 × t_period
40%
45%
6.25
60 ⁽³⁾
–0.175 × t_period ⁽⁴⁾
(1) All typical values are at 25°C and with a nominal supply.
(2) In TBID/NBID Modes Only, the maximum allowed TXCLK period is 33.33 ns.
(3) In TBID/NBID Modes Only, the minimum allowed TXCLK frequency is 30 MHz.
(4) In TBID/NBID Modes, when the TXCLK is in the 30 → 60 MHz range, this parameter becomes -0.10 × t_period
(5) In TBID/NBID Modes, when the TXCLK is in the 30→ 60 MHz range, this parameter becomes +0.10 × t_period
MAX UNIT
ps
ps
60%
55%
16.67⁽²⁾ ns
160 MHz
+0.175 × t_period(5) ps
TXCLK
t_PERIOD
V_IH(ac)
VDDQ/2
V_IL(ac)
t_SETUP
t_HOLD
t_SETUP
t_HOLD
V_IH(ac)
TXDATA VDDQ/2
V_IL(ac)
Figure 4-9. HSTL (DDR Timing Mode Only) Source Centered Data Input Timing Requirements
TXCLK
TXDATA
V_OH(ac)
VDDQ/2
V_OL(ac)
Tskew
Tskew
V_OH(ac)
VDDQ/2
V_OL(ac)
Figure 4-10. HSTL (DDR Timing Mode Only) Source Aligned Data Input Timing Requirements
80
Electrical Specifications
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