TLK3132 Datasheet, PDF (28/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
www.ti.com
2.7.11 Parallel Interface Clocking Modes
The TLK3132 supports source centered timing and source aligned DDR timing on the parallel receive
output bus. The TLK3132 also supports rising edge aligned and falling edge aligned SDR timing on the
parallel receive output bus. See Figure 2-18 for more details.
RXCLK
Source Centered (DDR)
RXD
RXC
t_SETUP
t_HOLD
Data
t_SETUP
t_HOLD
Data
Source Aligned (DDR)
RXD
RXC
Data
Falling Edge Aligned (SDR)
RXD
RXC
Data
Data
Data
Data
Rising Edge Aligned (SDR)
RXD
RXC
Data
Data
Figure 2-18. Receive Interface Timing – Source Centered/Aligned
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