TLK3132 Datasheet, PDF (25/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

www.ti.com
2.7.8 RNBI Mode (Reduced Nine Bit Interface)
TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
DATA CHANNEL
NUMBER
Channel 0
Channel 1
Table 2-10. RNBI – Lane To Functional Pin Mapping
TRANSMIT DATA 5 BITS
(INPUT)
TXD_[4:0]
TXD_[12:8]
RECEIVE DATA 5 BITS
(OUTPUT)
RXD_[4:0]
RXD_[12:8]
TRANSMIT CLOCK
(INPUT)
TXCLK_[0]
TXCLK_[1]
RECEIVE CLOCK
(OUTPUT)
RXCLK_[0]
RXCLK_[1]
TXCLK_[0]
TXD_[4:0]
DDR Source Centered Timing
(Nibble Order = 1 Default)
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
TXCLK_[0]
TXD_[4:0]
DDR Source Centered Timing
(Nibble Order = 0)
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
RXCLK_[0]
RXD_[4:0]
TXCLK_[0]
TXD_[4:0]
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
DDR Source Aligned Timing
(Nibble Order = 1 Default)
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
RXCLK_[0]
RXD_[4:0]
TXCLK_[0]
TXD_[4:0]
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
DDR Source Aligned Timing
(Nibble Order = 0)
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
RXCLK_[0]
RXCLK_[0]
RXD_[4:0]
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
RXD_[4:0]
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
Figure 2-15. RNBI – Individual Channel Byte Ordering – Channel 0 Example
Submit Documentation Feedback
Detailed Description
25