TLK3132 Datasheet, PDF (8/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
www.ti.com
2-81 DLL Offset Control ................................................................................................................ 53
2-82 TX0_DLL_STATUS ............................................................................................................... 53
2-83 TX1_DLL_STATUS ............................................................................................................... 53
2-84 RX0_DLL_STATUS............................................................................................................... 53
2-85 RX1_DLL_STATUS............................................................................................................... 53
2-86 CH0_TESTFAIL_ERR_COUNTER ............................................................................................. 53
2-87 CH1_TESTFAIL_ERR_COUNTER ............................................................................................. 53
2-88 STCI_CONTROL_STATUS...................................................................................................... 54
2-89 TESTCLK_CONTROL............................................................................................................ 54
2-90 BIDI_CMOS_CONTROL ......................................................................................................... 54
2-91 DEBUG_CONTROL .............................................................................................................. 54
2-92 DUTY_CYCLE_CONTROL ...................................................................................................... 54
3-1 Global Signals ..................................................................................................................... 63
3-2 JTAG Signals ...................................................................................................................... 64
3-3 MDIO Related Signals............................................................................................................ 64
3-4 Parallel Data Pins ................................................................................................................. 65
3-5 Serial Side Data/Clock Pins ..................................................................................................... 66
3-6 Miscellaneous Pins ............................................................................................................... 66
3-7 Voltage Supply and Reference Pins............................................................................................ 67
3-8 Jitter Cleaner Related Pins ...................................................................................................... 68
4-1 Driver Template Parameters..................................................................................................... 74
4-2 Parallel Interface – Valid Signal Operational Mode Definitions ............................................................. 76
4-3 TLK3132 Application Mode –vs– Interface Timing Mode Support.......................................................... 84
4-4 Worst Case Device Power Dissipation ......................................................................................... 86
A-1 Reference Clock Selection – Gigabit Ethernet Mode ........................................................................ 87
A-2 Reference Clock Selection – 1X/2X Fibre Channel Mode................................................................... 88
A-3 Reference Clock Selection – OBSAI Mode.................................................................................... 88
A-4 Reference Clock Selection – CPRI Mode...................................................................................... 89
A-5 Reference Clock Selection – 9/10 Bit SERDES Mode – Full Rate (SPEED[1:0] = 00).................................. 89
A-6 Reference Clock Selection – 9/10 Bit SERDES Mode – Half Rate (SPEED[1:0] = 01) ................................. 90
A-7 Reference Clock Selection – 9/10 Bit SERDES Mode – Quarter Rate (SPEED[1:0] = 10) ............................. 90
A-8 Reference Clock Selection – 8 Bit SERDES Mode – Full Rate (SPEED[1:0] = 00) ..................................... 91
A-9 Reference Clock Selection – 8 Bit SERDES Mode – Half Rate (SPEED[1:0] = 01) ..................................... 91
A-10 Reference Clock Selection – 8 Bit SERDES Mode – Quarter Rate (SPEED[1:0] = 10)................................. 91
C-1 Device Mode Configuration .................................................................................................... 100
C-2 Device Test Mode Pin Configuration.......................................................................................... 100
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