TLK3132 Datasheet, PDF (67/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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SIGNAL
DVDD
VDDO
VDDM
VDDQ
VREF1, VREF2
DGND
AVDD
AGND
VDDR
VDDT
VDDD
TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
Table 3-7. Voltage Supply and Reference Pins
LOCATION
E6, E8, F10,
F4, F5, G10, K10
K5, L2, L8, N2
F3, H13, K12, K4
G14
A3, A7, B11, B13
B6, D1, E10, E5,
E7, E9, F14, G11
E14, A11
A1, A9, B3, B4,
B7, C10, C13,
D5, E11, E13, F1,
F6, F7, F8, F9,
G6, G7, G8, G9,
H6, H7, H8, H9,
J10, J5, J6, J7, J8, J9,
K1, L14, P1, P14
K6, K8, K9, L11
M12, M3, M6, P10, P7
K11, L10, L4, L5, L6, L9,
M8, N12, N4, P12, P5, P9
K7, L7
L12, M7, N10, N5, N8
P11, P13, P4, P8
TYPE
DESCRIPTION
P
Digital Core Power Supply (1.2 V ±5%)
P
LVCMOS and Bias Power (2.5 V ±5%)
P
MDIO Power (2.5 V or 1.2 V ±5%)
HSTL Power (1.5/1.8 V)
P
1.5 V Operation Range: 1.4 V → 1.6 V
1.8 V Operation Range: 1.7V → 1.9 V
P
HSTL Reference Voltage (0.75 V or 0.9 V)
These signals should be equal to VDDQ divided by 2.
G
Digital Ground
P
Analog Power (1.2 V ±5%)
G
Analog Ground
P
SERDES Voltage Regulator Input (1.5 V -or- 1.8 V)
P
SERDES Termination Voltage (1.2 V)
P
SERDES Digital Power (1.2 V)
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Device Reset Requirements/Procedure
67