TLK3132 Datasheet, PDF (35/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
BIT(s)
1.3
1.2
1.1
1.0
Table 2-14. PHY_STATUS_1 (continued)
ADDRESS: 0x01
DEFAULT: 0x0101
NAME
DESCRIPTION
AN Ability
Read will return 0, indicating that Auto negotiation is not supported
Link Status
Read will return the Link Status and is valid only when device is in GMII/RGMII mode or when
bit 17.7 is set in Non-GMII/RGMII modes. Note: Link status will always indicate high when in
loopback. In remote loopback mode, the bit represents the normal bit function.
1 = Link UP
0 = Link DOWN
Jabber Detect
Always reads 0
Extended
Capability
Read will return 1 indicating extended register capability
ACCESS
RO
RO/LL
RO
RO
BIT(s)
2.15.0
Table 2-15. PHY_IDENTIFIER_1
ADDRESS: 0x02
NAME
OUI c:r
DESCRIPTION
Organizationally unique identifier.
DEFAULT: 0x4000
ACCESS
RO
BIT(s)
3.15:0
Table 2-16. PHY_IDENTIFIER_2
ADDRESS: 0x03
NAME
OUI c:r
DEFAULT: 0x50E0
DESCRIPTION
Device identifier. Manufacturer model and revision number
ACCESS
RO
BIT(s)
15.15
15.14
15.13
15.12
Table 2-17. PHY_EXT_STATUS
ADDRESS: 0x0F
NAME
1000Base-X FD
1000Base-X HD
1000Base-T FD
1000Base-T HD
DEFAULT: 0x8000
DESCRIPTION
Always reads 1, indicating device supports Full Duplex mode.
Read will return 0, writes will be ignored.
Read will return 0, writes will be ignored.
Read will return 0, writes will be ignored.
ACCESS
RO
RO
RO
RO
BIT(s)
16.15
16.11
16.10:9
16.8
Table 2-18. PHY_CH_CONTROL_1
ADDRESS: 0x10
DEFAULT: 0x0000
NAME
DESCRIPTION
Global write
When written as 1 the settings in 16.11:0 will affect all channels of one device
simultaneously.
When written as 0 the settings in 16.11:0 are only valid for the addressed
channel.
This value always reads zero.
Datapath reset control
1 = Resets channel logic excluding MDIO registers (Resets both Tx and Rx
datapaths)
Receive Parallel Output clock
select
00 = Selects respective channel SERDES TX clock (Default 2’b00)
01 = Selects Jitter cleaned clock(Selecting the jitter cleaned clock while the jitter
cleaner PLL is disabled is not recommended)
10 = Selects respective channel SERDES RX clock
11 = Reserved
Farend Loopback
Logically ORed with SLOOP
When asserted high the data presented at the serial receive interface is looped
back to the serial transmit interface of the same channel via the deserializer, the
serializer and if enabled the PCS function. If 1GX PCS is not enabled, the
incoming data rate must be frequency locked (ppm 0) with REFCLK.
Also referred to as remote loopback.
0 = Farend Loopback is disabled. (Default 1’b0)
1 = Farend loopback is enabled.
ACCESS
RW/SC
RW/SC
RW
RW
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