TLK3132 Datasheet, PDF (5/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
4-10 HSTL (DDR Timing Mode Only) Source Aligned Data Input Timing Requirements ..................................... 80
4-11 HSTL (SDR Timing Mode Only) Falling Edge Aligned (Rising Edge Sampled) Data Input Timing Requirements .. 81
4-12 HSTL (SDR Timing Mode Only) Rising Edge Aligned (Falling Edge Sampled) Data Input Timing Requirements .. 81
4-13 MDIO Read/Write Timing ........................................................................................................ 82
4-14 JTAG Timing....................................................................................................................... 83
4-15 HSTL I/O Schematic .............................................................................................................. 83
4-16 PACKAGE Information (Package Designator = ZEN)........................................................................ 85
A-1 Standard Based Jitter Cleaner/SERDES Provisioning ....................................................................... 92
A-2 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (2x) Provisioning ..................................................... 93
A-3 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (1x) Provisioning ..................................................... 94
A-4 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (0.5x) Provisioning................................................... 95
A-5 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (0.25x) Provisioning ................................................. 96
A-6 8 BIT SERDES Mode – Jitter Cleaner/SERDES (2x) Provisioning^(A) ...................................................... 96
A-7 8 BIT SERDES Mode – Jitter Cleaner/SERDES (1x) Provisioning^(A) ...................................................... 97
A-8 8 BIT SERDES Mode – Jitter Cleaner/SERDES (0.5x) Provisioning ...................................................... 97
A-9 Recovered Byte Clock Jitter Cleaner Mode ................................................................................... 98
B-1 Jitter Cleaner External Loop Filter .............................................................................................. 99
List of Figures
5