TLK3132 Datasheet, PDF (55/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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3 Device Reset Requirements/Procedure
TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
3.1 Gigabit Ethernet Mode (RGMII)
Note: All global registers must be accessed indirectly through Clause 22.
REFCLK frequency = 125 MHz, Serdes Data Rate = Half Rate, Mode = Transceiver, Edge Mode = Source
Centered Mode, RX_CLK[n] out = TXBCLK[n], Jitter Cleaner PLL Multiplier Ratio = 1X or Off
• Device Pin Setting(s) – Pin settings allow for maximum software configurability.
– Ensure CODE input pin is Low.
– Ensure PLOOP input pin is Low.
– Ensure SLOOP input pin is Low.
– Ensure SPEED [1:0] input pins are both High.
– Ensure ENABLE input pin is High.
– Ensure PRBS_EN input pin is Low.
• Reset Device
– Issue a hard or soft reset (RST_N asserted for at least 10 µs -or- Write 1’b1 to 0.15)
• Clock Configuration
– If using JCPLL (JCPLL 1X)
• JCPLL Mux Settings (see Figure 1-2)
– Select REFCLK input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b01 to 37120.15:14
– If Differential REFCLK used – Write 2’b00 to 37120.15:14
• Write 2’b11 to 37120.13:12 to select differential REFCLKP/N as RXBYTECLK
• Write 4’b0000 to 37120.11:8 to select jitter cleaned clock for SERDES TX/RX.
• Write 2’b11 to 37120.7:6 to select differential REFCLKP/N as delay stopwatch clock input
• Write 2’b00 to 37120.5:4 to select jitter cleaned clock for HSTL VTP 2x
• Write 2’b00 to 16.10:9 to select SERDES TX clock as RX_CLK output
• Write 16’h0081 to 37126 to set Charge pump control
• Write 16’h00A0 to 37128 to set TXRX output divider
• Clock Divide Settings (see Figure A-1)
– Write 7’b1000000 to 37124.14:8 to set REF_DIV to value of 1
– Write 1’b1 to 37124.15 REFDIV_EN to enable reference clock divider
– Write 7’h18 to 37124.6:0 to set FB_DIV to value of 24
– Write 1’b1 to 37124.7 FBDIV_EN to enable feedback divider
– Write 7’h18 to 37125.6:0 to set RXTX_DIV to value of 24
– Write 1’b1 to 37125.7 OUTDIV_EN to enable RXTX_DIV output divider
– Write 7’h0D to 37121.14:8 to set HSTL_DIV to value of 13
– Write 7’h06 to 37121.6:0 to set HSTL_DIV2 to value of 6
– Write 2’b11 to 36864.14:13 to set RX Loop Bandwidth
– Write 2’b11 to 36864.6:5 to set TX Loop Bandwidth
– Write 4’b0101 to 36864.11:8 to set MPY RX multiplier factor to 10
– Write 4’b0101 to 36864.3:0 to set MPY TX multiplier factor to 10
– Write 16’h5050 to 36865 SERDES_RATE_CONFIG_TX_RX to set Half Rate
– Write 3'b000 to 37127.14:12 to set control bits for VCO tail current to 0
– Write 1’b1 to 37127.15 to enable Jitter Cleaner
– Wait 50 ms in order for JCPLL to lock
– Else if using clock bypass mode (JCPLL Off)
• JCPLL Mux Settings (see Figure 1-2)
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Device Reset Requirements/Procedure
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