TLK3132 Datasheet, PDF (51/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

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TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
BIT(s)
37635.15
37635.14
37635.13
37635.12
37635.11:9
37635.7:5
37635.3
Table 2-75. HSTL_OUTPUT_VTP_CONTROL
ADDRESS: 0x9303
NAME
O_FORCE_UP_N
O_FORCE_UP_P
O_FORCE_DOWN_N
O_FORCE_DOWN_P
O_VTP_DRIVE[2:0]
O_FILTER_CONTROL[2:0]
O_LOCK
DEFAULT: 0x0640
DESCRIPTION
When set, increases NFET strength in all HSTL output cells . For TI
purposes Only
When set, increases PFET strength in all HSTL output cells . For TI
purposes Only
When set, decreases NFET strength in all HSTL output cells . For TI
purposes Only
When set, decreases PFET strength in all HSTL output cells . For TI
purposes Only
Drive strength control for HSTL output cells
3’b000 = 30% drive strength increase
3’b001 = 20% drive strength increase
3’b010 = 10% drive strength increase
3’b011 = Normal drive strength(default)
3’b100 = 10% drive strength decrease
3’b101 = 20% drive strength decrease
3’b110 = 30% drive strength decrease
3’b111 = 40% drive strength decrease
Filter Control
3’b000 = Impedance change filtering off
3’b001 = Update on 2 consecutive update requests
3’b010 = Update on 3 consecutive update requests(default)
3’b011 = Update on 4 consecutive update requests
3’b100 = Update on 5 consecutive update requests
3’b101 = Update on 6 consecutive update requests
3’b110 = Update on 7 consecutive update requests
3’b111 = Update on 8 consecutive update requests
Impedance Lock Control
When set, disables dynamic impedance control updates for HSTL output
cells
ACCESS
RW
RW
RW
RW
BIT(s)
37636.15
37636.14
37636.11
37636.7
37636.3
37636.2
Table 2-76. HSTL_GLOBAL_CONTROL
ADDRESS: 0x9304
NAME
HSTL power down control
HSTL Retrain
HSTL_CLK_EN
Voltage reference selection
VTP POWERSAVE
GP 3-state Control
DEFAULT: 0x0088
DESCRIPTION
When set, triggers HSTL power down sequence and places all HSTL cells
in power down state.
When set, triggers retraining of all HSTL inputs and outputs to match the
impedance. Retraining is triggered only when this bit value goes from 0 to
1. HSTL retraining should occur at the end of device provisioning.
HSTL impedance control clock (CLK2X) selection
1 = Uses MDC (MDIO clock) as CLK2X
0 = Uses clock generated from Jitter cleaner as CLK2X
1 = Internal voltage reference used for HSTL input signals
0 = External voltage reference used for HSTL input signals
When set, enables power save mode on HSTL VTP controllers
When set, 3-states GP outputs
ACCESS
RW
RW
RW
RW
RW
RW
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