TLK3132 Datasheet, PDF (64/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
www.ti.com
SIGNAL
TDI
TDO
TMS
TCK
TRST_N
LOCATION
K13
H14
K14
J12
M14
VOLTAGE
VDDO
VDDO
VDDO
VDDO
VDDO
Table 3-2. JTAG Signals
TYPE
DESCRIPTION
2.5 V LVCMOS
Input (Internal
Pullup)
JTAG Input Data. TDI is used to serially shift test data and test instructions
into the device during the operation of the test port.
2.5 V LVCMOS
Output
JTAG Output Data. TDO is used to serially shift test data and test
instructions out of the device during operation of the test port. When the JTAG
port is not in use, TDO is in a high impedance state.
2.5 V LVCMOS
Input (Internal
Pullup)
JTAG Mode Select. TMS is used to control the state of the internal test-port
controller.
2.5 V LVCMOS JTAG Clock. TCK is used to clock state information and test data into and out
Input
of the device during the operation of the test port.
2.5 V LVCMOS
Input (Internal
Pullup)
JTAG Test Reset. TRST_N is used to reset the JTAG logic into system
operational mode.
Table 3-3. MDIO Related Signals
SIGNAL
MDC
MDIO
PRTAD[4:0]
REFCLK
LOCATION VOLTAGE
TYPE
DESCRIPTION
1.2 V OR 2.5
G13
VDDM V LVCMOS Management Interface Clock This clock is used to sample the MDIO signal.
Input
Management Interface Data This bidirectional data line for MDIO Port is
1.2 V OR 2.5 _{sampled on the rising edge of MDC.}
F13
VDDM V LVCMOS
Input/ Output ^{THIS SIGNAL MUST BE EXTERNALLY PULLED UP TO VDDM. Consult}
IEEE802.3 Clause 22/45 for an appropriate resistance value.
Port Address Used to select Port ID in Clause 22 MDIO modes.
PRTAD[4:1] selects a block of two sequential Clause 22 port addresses. Each
L13
channel is implemented as a different port address, and can be accessed by
N13
2.5 V
setting the appropriate port address field within the Clause 22 MDIO transaction.
L3
N3
J11
VDDO
LVCMOS
Input
PRTAD[0] is not used functionally, but is needed for device testability with other
devices in the family of products.
Channel 0 responds to port address 0 within the block of two port addresses.
Channel 1 responds to port address 1 within the block of two port addresses.
Single Ended Reference Clock Single ended reference clock input. By default,
the differential reference clock (REFCLKP/N) is selected. This default value may
2.5 V
be changed by a mdio register (37120.15:14). The acceptable input frequency
K2
VDDO
LVCMOS _{range on this input signal is}
Input
50 MHz → 150 MHz.
Jitter performance is optimal when using the differential REFCLK input.
64
Device Reset Requirements/Procedure
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