TLK3132 Datasheet, PDF (4/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
www.ti.com
List of Figures
1-1 System Block Diagram – PCS................................................................................................... 10
1-2 Block Diagram – TLK3132 Clocking Architecture............................................................................. 11
2-1 Dual 10-Bit SERDES Application ............................................................................................... 13
2-2 1000Base-X – Remote (Serial) Loopback Application ....................................................................... 13
2-3 1000Base-X – Local (Parallel ) Loopback Application ....................................................................... 13
2-4 Custom Independent Configuration Application............................................................................... 14
2-5 TLK3132 Block Diagram ......................................................................................................... 15
2-6 Detailed 1000Base-X Core Block Diagram .................................................................................... 16
2-7 Block Diagram of SERDES Core ............................................................................................... 17
2-8 RGMII – Individual Channel Byte Ordering – Channel 0 Example ......................................................... 18
2-9 RTBI – Individual Channel Byte Ordering – Channel 0 Example........................................................... 19
2-10 TBI – Individual Channel Byte Ordering – Channel 0 Example............................................................. 20
2-11 GMII – Individual Channel Byte Ordering – Channel 0 Example ........................................................... 21
2-12 EBI – Individual Channel Byte Ordering – Channel 0 Example............................................................. 22
2-13 REBI – Individual Channel Byte Ordering – Channel 0 Example........................................................... 23
2-14 NBI – Individual Channel Byte Ordering – Channel 0 Example ............................................................ 24
2-15 RNBI – Individual Channel Byte Ordering – Channel 0 Example .......................................................... 25
2-16 TBID – Individual Channel Byte Ordering – Channel 0 Example........................................................... 26
2-17 NBID – Individual Channel Byte Ordering – Channel 0 Example .......................................................... 27
2-18 Receive Interface Timing – Source Centered/Aligned ....................................................................... 28
2-19 Transmit Interface Timing ........................................................................................................ 29
2-20 Example High-Speed I/O AC Coupled Mode.................................................................................. 30
2-21 Output Differential Voltage with 1-Tap FIR De-Emphasis ................................................................... 30
2-22 CL22 – Management Interface Read Timing⁽¹⁾................................................................................ 32
2-23 CL22 - Management Interface Write Timing................................................................................... 32
2-24 CL22 – Indirect Address Method – Address Write............................................................................ 32
2-25 CL22 – Indirect Address Method – Data Write................................................................................ 32
2-26 CL22 – Indirect Address Method – Address Write............................................................................ 33
2-27 CL22 – Indirect Address Method – Data Read⁽¹⁾ ............................................................................. 33
3-1 Device Pinout Diagram – (Top View)........................................................................................... 68
4-1 Transmit Output Waveform Parameter Definitions ........................................................................... 74
4-2 Transmit Template ................................................................................................................ 74
4-3 Receive Template................................................................................................................. 75
4-4 Input Jitter .......................................................................................................................... 75
4-5 HSTL (DDR Timing Mode Only) Source Centered Output Timing Requirements........................................ 78
4-6 HSTL (DDR Timing Mode Only) Source Aligned Output Timing Requirements .......................................... 78
4-7 HSTL (SDR Timing Mode Only) Rising Edge Aligned Output Timing Requirements .................................... 79
4-8 HSTL (SDR Timing Mode Only) Falling Edge Aligned Output Timing Requirements.................................... 79
4-9 HSTL (DDR Timing Mode Only) Source Centered Data Input Timing Requirements ................................... 80
4
List of Figures
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