TLK3132 Datasheet, PDF (68/103 Pages) Texas Instruments – 2-Channel Multi-Rate Transceiver

TLK3132
2-Channel Multi-Rate Transceiver
SLLS956 – DECEMBER 2008
www.ti.com
SIGNAL
REFCLKP/
REFCLKN
VDDA_VCO
VSSA_VCO
VDDA_CP
VSSA_CP
VDD_CML
VSS_CML
VDD_PLL
VSS_PLL
VCO_TL_TST
TST_OUT
CP_OUT
VTUNE
LOCATION
J1
H1
G4
G2
J4
H4
H3
J3
G5
H5
J2
G1
G3
H2
Table 3-8. Jitter Cleaner Related Pins
TYPE
I
P
G
P
G
P
G
P
G
Analog Input
Analog
Input/Output
Analog Output
Analog Input
DESCRIPTION
Differential Reference Clock Inputs
By default, the differential reference clock (REFCLKP/N) is selected.
This default value may be changed by a mdio register (37120.15:14).
Must Be Externally AC Coupled
REFCLKP – DPECL REFCLK P Input
REFCLKN – DPECL REFCLK N Input
Acceptable input frequency range is 50 MHz → 375 MHz.
Jitter performance is optimal when using the differential REFCLK input.
Jitter Cleaner – VCO Supply – 1.2 V
Jitter Cleaner Ground
Jitter Cleaner – Charge Pump – 1.2 V
Jitter Cleaner Ground
Jitter Cleaner – REFCLKP/N Input Supply – 1.2 V
Jitter Cleaner Ground
Jitter Cleaner Digital Power (1.2 V)
Jitter Cleaner Ground
VCO Testability Input. This signal should be grounded in the application.
Jitter Cleaner Testability Pin. This signal should be left open (unconnected) in the
application.
Charge Pump Output. If the internal Jitter Cleaner PLL is used, this signal should be
connected to the input of the external loop filter (See Figure B-1). If the internal Jitter
Cleaner PLL is not used, this node should be left open (unconnected).
LC VCO Bias Voltage. This signal should be connected to the output of the external
loop filter if the Jitter Cleaner PLL is used (Figure B-1). If the internal Jitter Cleaner
PLL is not used, this node should be grounded.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
DGND
RXD_0
VDDQ
RXD_1
RXC_4 RXCLK_0 VDDQ TXD_13 DGND RES4
VREF2 TXD_11 TXD_10 TXD_8
B
RXD_7
RXD_3
DGND
DGND RXCLK_1 VDDQ DGND TXD_15 TXC_5 TXD_12 VDDQ
TXD_9 VDDQ
TXD_7
C
RXD_9
RXD_4
RXD_6
RXC_5
RES1
RXC_1 RXD_2 VPP TXD_14 DGND
TXD_3
TXD_0
DGND
TXC_0
D
VDDQ
RXD_8
RXD_11
RXD_13
DGND
RXD_5 RXC_0 VPP TXC_4 TXCLK_1 TXD_6 TXD_1 TXC_1
RES3
E RXD_10
RXD_12
RXD_14
RXD_15
VDDQ
DVDD VDDQ DVDD VDDQ VDDQ
DGND
TXD_5 DGND VREF1
F
DGND
SPEED1
VDDO
DVDD
DVDD
DGND DGND DGND DGND DVDD
TXD_4 TXD_2
MDIO
VDDQ
G TST_OUT VSSA_VCO
CP_OUT VDDA_VCO VDD_PLL DGND DGND DGND DGND DVDD
VDDQ TXCLK_0 MDC
VDDM
H REFCLKN VTUNE
VDD_CML VSSA_CP VSS_PLL DGND DGND DGND DGND GPO3
GPO1
GPO2
VDDO
TDO
J REFCLKP VCO_TL_TST VSS_CML VDDA_CP DGND
DGND DGND DGND DGND DGND PRTAD0
TCK
SLOOP SPEED0
K
DGND
REFCLK
CODE
VDDO
DVDD
AVDD VDDR AVDD AVDD DVDD
AGND
VDDO
TDI
TMS
L
GPO4
DVDD
PRTAD2
AGND
AGND
AGND VDDR DVDD AGND AGND
AVDD
VDDT PRTAD4 DGND
M PRBS_EN ENABLE
AVDD
TDN0
TDP0
AVDD VDDT AGND RDN0 AMUX1
RDP1
AVDD PLOOP TRST_N
N
RST_N
DVDD
PRTAD1
AGND
VDDT
AMUX0 TDN1 VDDT RDP0
VDDT
RDN1
AGND PRTAD3
GPI1
P
DGND
GPO0
TESTEN
VDDD
AGND
TDP1 AVDD VDDD AGND AVDD
VDDD
AGND
VDDD
DGND
Figure 3-1. Device Pinout Diagram – (Top View)
68
Device Reset Requirements/Procedure
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