HD6417751RBP240V Datasheet, PDF (987/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

22. PCI Controller (PCIC)
Bit 2—INTA Output (INTA): Software control of INTA (valid only when PCIC is not host)
Bit 2: INTA
0
1
Description
INTA pin at Hi-Z (driven to High by pull-up resistor)
Assert INTA (Low output)
(Initial value)
Bit 1—PCIRST Output Control (RSTCTL): Controls the PCIRST output. This field is reset
only at a power-on reset. Do not use the field when the PCIC is non-host.
Bit 1: PCIRST
0
1
Description
Negate PCIRST (High output)
Assert PCIRST (Low output)
(Initial value)
Bit 0—PCIC Internal Register Initialization Control Bit (CFINIT): After the SH initializes
the PCI registers, setting this bit enables access from the PCI bus. During initialization, no bus
privileges are granted to other devices on the PCI bus while operating as the host. When operating
not as the host, a retry is returned without the access from the PCI bus being accepted.
Bit 0: CFINIT
0
1
Description
Initialization busy
Initialization complete
(Initial value)
Rev.4.00 Oct. 10, 2008 Page 887 of 1122
REJ09B0370-0400