HD6417751RBP240V Datasheet, PDF (881/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

19. Interrupt Controller (INTC)
Table 19.5 Interrupt Request Sources and IPRA–IPRD Registers
Bits
Register
15–12
11–8
7–4
3–0
Interrupt priority register A
Interrupt priority register B
TMU0
WDT
TMU1
REF*¹
TMU2
SCI1
RTC
Reserved*²
Interrupt priority register C
GPIO
DMAC
SCIF
H-UDI
Interrupt priority register D
IRL0
IRL1
IRL2
IRL3
Notes: 1. REF is the memory refresh unit in the bus state controller (BSC). See section 13, Bus
State Controller (BSC), for details.
2. Reserved bits: These bits are always read as 0 and should always be written with 0.
As shown in table 19.5, four on-chip peripheral modules are assigned to each register. Interrupt
priority levels are established by setting a value from H'F (1111) to H'0 (0000) in each of the four-
bit groups: 15–12, 11–8, 7–4, and 3–0. Setting H'F designates priority level 15 (the highest level),
and setting H'0 designates priority level 0 (requests are masked).
19.3.2 Interrupt Control Register (ICR)
The interrupt control register (ICR) is a 16-bit register that sets the input signal detection mode for
external interrupt input pin NMI and indicates the input signal level at the NMI pin. This register
is initialized by a power-on reset or manual reset. It is not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
Bit name: NMIL
MAI
—
—
—
—
NMIB NMIE
Initial value: 0/1*
0
0
0
0
0
0
0
R/W: R
R/W
—
—
—
—
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Bit name: IRLM
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
—
—
—
—
—
—
—
Note: * 1 when NMI pin input is high, 0 when low.
Rev.4.00 Oct. 10, 2008 Page 781 of 1122
REJ09B0370-0400