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HD6417751RBP240V Datasheet, PDF (151/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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2. Programming Model
2.2.2 General Registers
Figure 2.3 shows the relationship between the processor modes and general registers. The SH-4
has twenty-four 32-bit general registers (R0_BANK0âR7_BANK0, R0_BANK1âR7_BANK1,
and R8âR15). However, only 16 of these can be accessed as general registers R0âR15 in one
processor mode. The SH-4 has two processor modes, user mode and privileged mode, in which
R0âR7 are assigned as shown below.
⢠R0_BANK0âR7_BANK0
In user mode (SR.MD = 0), R0âR7 are always assigned to R0_BANK0âR7_BANK0.
In privileged mode (SR.MD = 1), R0âR7 are assigned to R0_BANK0âR7_BANK0 only when
SR.RB = 0.
⢠R0_BANK1âR7_BANK1
In user mode, R0_BANK1âR7_BANK1 cannot be accessed.
In privileged mode, R0âR7 are assigned to R0_BANK1âR7_BANK1 only when SR.RB = 1.
Rev.4.00 Oct. 10, 2008 Page 51 of 1122
REJ09B0370-0400
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